Patents by Inventor Mun Low

Mun Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8330159
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
  • Publication number: 20090114912
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
  • Publication number: 20080017976
    Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.
    Type: Application
    Filed: August 8, 2007
    Publication date: January 24, 2008
    Inventors: Yin Lai, Choong Chee, Edward Then, Cheong Ng, Mun Low
  • Publication number: 20060214311
    Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.
    Type: Application
    Filed: September 30, 2003
    Publication date: September 28, 2006
    Inventors: Yin Lai, Choong Chee, Edward Then, Cheong Ng, Mun Low