Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor substrate within a space having a first width, a gate insulating layer which has a width wider than the first width and may be formed on an upper side of the channel area on the semiconductor substrate, a gate which may be formed with the first width on the gate insulating layer, and a spacer including a first spacer formed at both sides of the gate insulating layer and a second spacer formed at sidewalls of the gate.

Abstract: A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate.

Abstract: Disclosed are a capacitor and a method of manufacturing the same. The capacitor includes a plurality of polysilicon electrodes spaced apart from each other at a predetermined distance on a substrate, a dielectric layer between the polysilicon electrodes and having an air layer or void therein, a silicide on each polysilicon electrode, and a conductive contact electrically connected to the silicide.

Abstract: A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second gate pattern is wider than the first gate pattern. Forming sidewall spacers at both sides of the first gate pattern and the second gate pattern, such that spaces are formed between the sidewall spacers and the first gate pattern below the second gate pattern.

Abstract: A semiconductor device and a method thereof that maximizes DC and AC parameter properties of a MOS transistor having a buried channel. The device includes a semiconductor substrate having a device separation film, a gate pattern formed over the semiconductor substrate, a well region formed in the semiconductor substrate, the well region including a first doped region formed at a first predetermined depth, a second doped region formed at a second predetermined depth and a third doped region formed at a third predetermined depth, trenches formed at a source/drain region around the gate pattern, and a source/drain formed in the trenches. In accordance with embodiments, the first predetermined depth is lower than the second and third predetermined depths and the third predetermined depth is greater than the second predetermined depth.

Abstract: A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate having a plurality of isolation areas formed therein, the isolation areas defining an active region, a gate electrode formed on the active region, spacers formed on sides of the gate electrode, a source region formed in the substrate at a side of the spacer formed at a first side of the gate electrode, a drain region formed in the substrate at a side of the spacer formed on a second side of the gate electrode, and lightly doped drain regions formed in the substrate below the spacer.

Abstract: Provided are a capacitor of a semiconductor device having an increased capacitance within a minimum area, and a fabrication method thereof. The capacitor includes a first electrode on a substrate, a first insulator on the first electrode, a second electrode on the first insulator, a second insulator on the second electrode where the second insulator is in contact with the first insulator, and a third electrode on the second insulator where the third electrode is in contact with the first electrode. In embodiments, the capacitance can be desirably adjusted within a limited area by alternately overlaying electrodes and insulator layers connected at alternating sides to the electrode or insulator layer below, which makes it possible to design the semiconductor device flexibly and maximize the capacitance.

Abstract: Embodiments relate to an ion implantation method wherein a semiconductor substrate is divided into a core region, a high voltage region, and an I/O region. The core region and the I/O region are divided into a PMOS transistor region for forming PMOS transistors and an NMOS transistor region for forming NMOS transistors. The ion implantation method includes performing a first ion implantation process employing a first process condition on the NMOS transistor region of the substrate using a first mask, thus setting threshold voltages for the NMOS transistor region of the I/O region and for the high voltage region at the same time. A second ion implantation process employs a second process condition on the NMOS transistor region of the substrate using a second mask, thus setting a threshold voltage for the core region.

Abstract: A method for forming an LDD structure of a gate electrode of a MOSFET. The gate electrode may be formed by sequentially depositing a gate oxide layer and a poly silicon layer over a semiconductor substrate. A photo resist pattern may be formed over the resultant structure. A gate electrode may be formed by an etch using the photo resist pattern as a mask. An LDD area may be formed by ion implanting a low-concentration dopant using the gate electrode as a mask. After depositing a spacer layer over the upper surface of the substrate, a spacer may be formed by etching. A source/drain area may be formed by ion implanting a high-concentration dopant using the gate electrode and the spacer as a mask. A portion of the gate oxide layer where the gate oxide layer and the LLD area overlap may be removed by performing an etch process over the resultant structure.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor substrate within a space having a first width, a gate insulating layer which has a width wider than the first width and may be formed on an upper side of the channel area on the semiconductor substrate, a gate which may be formed with the first width on the gate insulating layer, and a spacer including a first spacer formed at both sides of the gate insulating layer and a second spacer formed at sidewalls of the gate.