Abstract: A power-on circuit which may generate a power-on signal that is insensitive to the rising speed of an I/O voltage or core voltage. A power-on signal may be generated according to current drive capabilities of NMOS and PMOS transistors based on the I/O voltage or core voltage. A power-on circuit may control an I/O voltage when the level of a core voltage is lower than the I/O voltage.

Abstract: A level shifter output buffer circuit which converts a first operating voltage into a second operating voltage and outputs a converted voltage to an output terminal. A level shifter output buffer circuit may include at least one of: a first level shifter configured to receive an enable signal as an input having a first operating voltage; a second level shifter configured to receive a data signal as an input having a first operating voltage; a pull-up transistor configured to output a second operating voltage to an output terminal based on the output of a first level shifter and a second level shifter.

Abstract: An analog-to-digital converter is provided. The analog-to-digital converter capable of increasing the processing speed of the converter by using a number of SAR registers.

Abstract: In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU memory capable of performing a pseudo replacement policy and supporting multi-port required for operating various blocks included in the microprocessor. The LRU memory comprises an address decoding block for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD and a WRITE.sub.-- WORD in response to the first phase and a second phase of the CLOCK signal, respectively; an LRU storing block; a way hit decoding block for decoding a WAY.sub.-- HIT to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying block for latching a READ.sub.-- DATA from the LRU storing block to produce a DETECTED DATA and modifying it in response to the MODIFY CONTROL signal so as to produce a WRITE.sub.

Abstract: An apparatus serves to map internal registers into I/O addresses to select an internal register and perform read and write operations in the I/O address space of the PCMCIA host adapter, using the index mapping mechanism. The apparatus according to the present invention includes a plurality of internal registers for storing an input data, being arranged in the PCMCIA card; a plurality of first AND gates for producing a first control signal in response to index signals from an index register; a plurality of second AND gates for producing a register enabling signal in response to the first control signal and a data write signal from CPU; and a plurality of AND gates means for producing a third control signal outputting data stored in the internal register.