Abstract: A display panel and a display device are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a substrate, an array structure layer, a color resist layer, a pixel electrode layer, and a column spacer layer. The column spacer layer includes at least one spacer column, the color resist layer includes at least one supporting color resist block supporting the spacer column, a supporting compensation block is disposed on one side of any of the supporting color resist blocks, the supporting compensation block is disposed on the array structure layer, and the spacer column is disposed on the supporting color resist block and the supporting compensation block.

Abstract: The present invention provides a low-latency thin film transistor, an array substrate, and a display panel. The low-latency thin film transistor includes a gate, an active layer disposed on a side of the gate, and a source and a drain disposed above the gate, and the source and the drain are respectively connected to the active layer, wherein in a direction perpendicular to the active layer, at least part of an orthographic projection of the drain is located outside an orthographic projection of the gate.

Abstract: An array substrate and a display panel are provided. The array substrate includes one or more sub-pixels, and one or more connecting members corresponding to the first sub-pixels. A layer where the connecting members are located is insulated from the source/drain layer. Data lines connected to the first sub-pixels include first sub-data lines adjacent to the first sub-pixels. Both ends of each of the connecting members are connected to a corresponding first sub-data line through via holes. This improves a charging rate of sub-pixels.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a substrate, an array structure layer, a color resist layer, a pixel electrode layer, and a column spacer layer. The column spacer layer includes at least one spacer column, the color resist layer includes at least one supporting color resist block supporting the spacer column, a supporting compensation block is disposed on one side of any of the supporting color resist blocks, the supporting compensation block is disposed on the array structure layer, and the spacer column is disposed on the supporting color resist block and the supporting compensation block.