Abstract: To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated circuit, a trace which is not present on trace grids to a position above the trace grids; a pattern correction section for making a correction to the pattern; and a trace pitch optimization section for optimizing a trace pitch between traces forming a pattern corrected by the pattern correction section.

Abstract: According to the present invention, timing information, connection information and physical information are received, and at the weighting determination step, the degree to which a cell can move is weighted. Then, at the movement range determination step, the movement enabled range of the cell is determined, and whether or not a cell placement area is available is decided. When it is decided that a cell placement area is available, the processing advances either to the cell movement area extension step or to the cell placement area acquisition step. Thereafter, an automatic, optimal placement process is performed for the cell.

Abstract: To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated circuit, a trace which is not present on trace grids to a position above the trace grids; a pattern correction section for making a correction to the pattern; and a trace pitch optimization section for optimizing a trace pitch between traces forming a pattern corrected by the pattern correction section.

Abstract: In a layout design, there are executed a step 201 of defining a permitted connecting relationship of an interface signal to be transmitted across different power supplies, a step 202 of extracting the interface signal between the different power supplies based on information about each of the power regions and information about a cell connection and optimizing a circuit in such a manner that the connecting relationship of the interface signal between the different power supplies is set to be one-to-one, a logic cell arranging step 203, a step 204 of verifying whether a logic cell of the interface signal between the different power supplies is arranged in a correct power region or not, an arrangement synthesizing step 205, a step 206 of confirming a timing and a slew before wiring, an arrangement correcting step 207, and a wiring step 208. Consequently, it is possible to carry out the verification between the different power supplies in consideration of physical information as well as logic information.