Patents by Inventor Muneharu Morioka
Muneharu Morioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8552542Abstract: A lead frame or semiconductor device and a method of manufacturing the same in which where the unit lead frame of each semiconductor device after dicing was located in a lead frame before dicing can be known without an additional manufacturing step. The lead frame includes a plurality of unit lead frames each having a die pad, suspension leads coupled to the die pad, and leads formed around the die pad. An identification mark including at least one of a penetrating groove, recess, and convex is formed in at least one of the die pad, suspension leads, and leads. The identification mark of a first unit lead frame and the identification mark of a second unit lead frame are different from each other at least either in location in the unit lead frame or in shape.Type: GrantFiled: August 15, 2012Date of Patent: October 8, 2013Assignee: Renesas Electronics CorporationInventor: Muneharu Morioka
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Publication number: 20130069214Abstract: A lead frame or semiconductor device and a method of manufacturing the same in which where the unit lead frame of each semiconductor device after dicing was located in a lead frame before dicing can be known without an additional manufacturing step. The lead frame includes a plurality of unit lead frames each having a die pad, suspension leads coupled to the die pad, and leads formed around the die pad. An identification mark including at least one of a penetrating groove, recess, and convex is formed in at least one of the die pad, suspension leads, and leads. The identification mark of a first unit lead frame and the identification mark of a second unit lead frame are different from each other at least either in location in the unit lead frame or in shape.Type: ApplicationFiled: August 15, 2012Publication date: March 21, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Muneharu MORIOKA
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Publication number: 20110266661Abstract: A semiconductor device is manufactured using a lead frame for a mold array package (MAP) where multiple mount parts are arranged in the shape of an array, each configured to have a semiconductor chip mounted thereon. Multiple leads for coupling to the semiconductor chip are formed in each of the mount parts of the lead frame. The tips of the leads are mutually coupled by tie bars thinner than the leads. A dummy lead having a slot coupling to the tie bar is formed on a portion corresponding to a portion further outside the tie bar and corresponding to a portion where the lead is formed in the mount parts at predetermined locations among the mount parts. Once the resin is supplied, air in a tie bar part is pushed out into the slot of the dummy lead; therefore, generation of void in the tie bar part can be controlled.Type: ApplicationFiled: May 2, 2011Publication date: November 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Muneharu MORIOKA
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Publication number: 20100290202Abstract: A semiconductor package comprises a conduction member, a semiconductor chip mounted on and electrically connected to the conduction member, and a sealing body configured to seal the conduction member and the semiconductor chip. The conduction member comprises a power supply section configured to supply a power voltage to said semiconductor chip, a ground section configured to supply a ground voltage to the semiconductor chip, and a signal section connected to a signal terminal of the semiconductor chip. The power supply section, the ground section, and the signal section are arranged so as not to overlap each other. At least a part of said ground section is exposed on an under surface of the sealing body. The power supply section comprises an exposed region of which bottom surface is exposed on the under surface, and a plurality of power hanging-pin region configured to extend to a side of the sealing body from the exposed region.Type: ApplicationFiled: May 4, 2010Publication date: November 18, 2010Applicant: Renesas Electronics CorporationInventors: Hideki Sasaki, Kenji Nishikawa, Muneharu Morioka
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Publication number: 20100055844Abstract: A method of manufacturing a semiconductor device, which is capable of easily removing a sealing sheet building up terminal surfaces of leads, includes arranging, on molds, terminal surfaces of leads in a lead frame on which semiconductor elements are mounted so as to come in contact with a sealing sheet, pouring a resin into the molds to form a resin sealed body including the semiconductor elements, and cleaning the resin sealed body, and the cleaning of the resin sealed body ravels the sealing sheet by a cleaning solvent and removes the sealing sheet.Type: ApplicationFiled: August 20, 2009Publication date: March 4, 2010Applicant: NEC Electronics CorporationInventor: Muneharu Morioka
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Patent number: 7556985Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: October 14, 2005Date of Patent: July 7, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 7064047Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: July 19, 2004Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20060030127Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: October 14, 2005Publication date: February 9, 2006Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6987054Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: March 15, 2002Date of Patent: January 17, 2006Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6881611Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.Type: GrantFiled: August 8, 2000Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
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Patent number: 6875638Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: GrantFiled: March 19, 2002Date of Patent: April 5, 2005Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Publication number: 20040259346Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6784542Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: July 15, 2003Date of Patent: August 31, 2004Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20040053444Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: ApplicationFiled: August 29, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Patent number: 6700198Abstract: In order to improve adhesion between a plated film which functions as an external connection terminal of a semiconductor device and a surface of a resin protuberance and to improve reliability, a carrier substrate includes a metal substrate which is shaped into a sheet form, to which a semiconductor chip is fixed, and which is removed before the semiconductor device is completed, a recess formed at a position of the metal substrate corresponding to the resin protuberance and having a rugged bottom surface and/or a rugged side surface, and a plated film formed on the inner surface of the recess.Type: GrantFiled: October 5, 2001Date of Patent: March 2, 2004Assignees: Shinko Electric Industries Co., Ltd., Fujitsu LimitedInventors: Hideki Toya, Mitsuyoshi Imai, Masaki Sakaguchi, Naoki Yamabe, Mamoru Suwa, Toshiyuki Motooka, Hideharu Sakoda, Muneharu Morioka
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Patent number: 6693029Abstract: A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so that the conductive metal film covers the via-hole on one side of the first part; using an electrolytic plating process, where the conductive metal Film is used as an electrode, to form a metal via member within the via hole and to form an inter-layer wire; and removing an entirety of the conductive metal film without removing the inter-layer formed by the electrolytic plating process; repeating steps (a)-(e) for a second part; and thereafter attaching the first part to the second part.Type: GrantFiled: December 28, 2001Date of Patent: February 17, 2004Assignee: Fujitsu LimitedInventors: Makoto Iijima, Masaru Nukiwa, Seiji Ueno, Muneharu Morioka
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Publication number: 20040012088Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: July 15, 2003Publication date: January 22, 2004Applicant: FUJITSU LIMITED,Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6657282Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: March 15, 2002Date of Patent: December 2, 2003Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6573600Abstract: A multilayer wiring substrate includes differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.Type: GrantFiled: March 27, 2001Date of Patent: June 3, 2003Assignee: Fujitsu LimitedInventors: Atsushi Kikuchi, Makoto Iijima, Yoshihiko Ikemoto, Muneharu Morioka, Yoshiyuki Kimura
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Publication number: 20030087483Abstract: A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and wiring layers formed therein are interconnected by means of vias. Each of the vias consisting of a via-hole which is formed penetrating both the organic insulation substrate layers and the filmy adhesive layers and a metal via member 26 which is provided in the via-hole and made of an identical material. A method of manufacturing the multi-flexible substrate for the semiconductor device is also disclosed.Type: ApplicationFiled: December 28, 2001Publication date: May 8, 2003Applicant: FUJITSU LIMITEDInventors: Makoto Iijima, Masaru Nukiwa, Seiji Ueno, Muneharu Morioka