Abstract: A method for manufacturing a semiconductor device having steps of forming an amorphous semiconductor on a substrate having an insulating surface; patterning the amorphous semiconductor to form plural first island-like semiconductors; irradiating a linearly condensed laser beam on the plural first island-like semiconductors while relatively scanning the substrate, thus crystallizing the plural first island-like semiconductors; patterning the plural first island-like semiconductors that have been crystallized into to form plural second island-like semiconductors; forming plural transistors using the plural second island-like semiconductors; and forming a unit circuit using a predetermined number of the transistors, where the second island-like semiconductors used for the predetermined number of the transistors are formed from the first island-like semiconductors that are different from each other.

Abstract: A gray-scale power supply line supplied to a source signal line driving circuit is made only one system, and each of D/A conversion circuits drives source signal lines in which three source signal lines corresponding to RGB are made a unit and the number of which is a multiple of 3. The periods in which respective source line selecting circuits select source signal lines corresponding to respective colors of the RGB are made synchronous with each other, and the power supply voltage applied to the gray-scale power supply line is changed in one horizontal writing period, so that power supply voltages corresponding to R, G and B are respectively applied to the gray-scale power supply line in periods while the source signal lines of R, G and B are respectively selected.

Abstract: The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

Abstract: In a driving circuit of a digital gradation system semiconductor display device, one D/A conversion circuit 208 is provided for a plurality of source signal lines, and the respective source signal lines are driven in a time-division manner. By this, the number of the D/A conversion circuits 208 in the driving circuit can be decreased, and miniaturization of the semiconductor display device can be achieved.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A compact level shifter is provided, which has a low consumption power and speedy operation, capable of easily performing a level conversion of voltage levels having a large difference. A voltage regulating circuit (10a), a P channel MOS, electric field effect transistor (hereinafter referred to as PMOST), a PMOST (103). and an N channel MOS electric field effect transistor (hereinafter referred to as NMOST) (105) are connected in series between 2 power sources. Similarly, a voltage regulating circuit (10b), a PMOST (102), a PMOST (104), and an NMOST (106) are connected in series between 2 power sources. During the flow of a penetrating current in a transient period of a level conversion operation, a power source voltage is effectively reduced by the above-mentioned voltage regulating circuit, whereby the level conversion of the voltage level having a large difference is made easy.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to an input electrode of a TFT (101), a non-inverting output signal is outputted from an output electrode of the TFT (101) and an inverting output signal is outputted from output electrodes of TFTs (102 and 103). Two line outputs of non-inversion and inversion are obtained. Thus, when a buffer located in a subsequent stage is operated, a period for which a direct current path is produced between a high potential and a low potential of a power source can be shortened, thereby contributing to reduction in a consumption current.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

Abstract: A pixel having a structure in which low voltage drive is possible is provided by a simple process. A digital image signal input from a source signal line is input to the pixel through a switching TFT. At this point, a voltage compensation circuit amplifies the voltage amplitude of the digital image signal or transforms the amplitude, and applies the result to a gate electrode of a driver TFT. On-off control of TFTs within the pixel can thus be performed normally even if the voltage of a power source for driving gate signal lines becomes lower.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A drive circuit of a display device, which comprise only single conductive TFTs and in which amplitude of an output signal is normal, is provided.

Abstract: The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node &agr; is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: A compact level shifter is provided, which has a low consumption power and speedy operation, capable of easily performing a level conversion of voltage levels having a large difference. A voltage regulating circuit (10a), a P channel MOS, electric field effect transistor (hereinafter referred to as PMOST), a PMOST (103). and an N channel MOS electric field effect transistor (hereinafter referred to as NMOST) (105) are connected in series between 2 power sources. Similarly, a voltage regulating circuit (10b), a PMOST (102), a PMOST (104), and an NMOST (106) are connected in series between 2 power sources. During the flow of a penetrating current in a transient period of a level conversion operation, a power source voltage is effectively reduced by the above-mentioned voltage regulating circuit, whereby the level conversion of the voltage level having a large difference is made easy.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.