Abstract: A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region.

Abstract: To test a memory operation at as high speeds as high clock frequencies only with low clock frequencies. A semiconductor device according to an embodiment of the present invention includes: a clock output part; and a delay circuit, the clock output part setting a first state in accordance with an input of a first clock, setting a second state in accordance with an input of a delay clock from the delay circuit, and setting a third state in accordance with an input of a second clock, and the delay circuit delaying the first clock to output the delayed first clock as the delay clock. With this configuration, it is possible to test precharge and read/write access processings at as high operational speeds as high clock frequencies.

Abstract: In synchronization with a PLL clock PCK having a frequency four times that of an external clock ECK, n number of internal addresses IAD including an external address EAD are generated and, in synchronization with the PLL clock PCK, n bits of internal write data ITD are generated to be written into a RAM macro 12. Thereafter, the external address EAD is latched, n number of the internal addresses IAD including the external address EAD are generated in synchronization with the PLL clock PCK, n bits of internal read data ITQ corresponding to n number of the internal addresses IAD are read from the RAM macro 12 in synchronization with the PLL clock PCK and the internal read data ITQ corresponding to the internal address IAD which coincides with a latch address LAD among n number of the internal addresses IAD is outputted.

Abstract: To test a memory operation at as high speeds as high clock frequencies only with low clock frequencies. A semiconductor device according to an embodiment of the present invention includes: a clock output part; and a delay circuit, the clock output part setting a first state in accordance with an input of a first clock, setting a second state in accordance with an input of a delay clock from the delay circuit, and setting a third state in accordance with an input of a second clock, and the delay circuit delaying the first clock to output the delayed first clock as the delay clock. With this configuration, it is possible to test precharge and read/write access processings at as high operational speeds as high clock frequencies.

Abstract: In synchronization with a PLL clock PCK having a frequency four times that of an external clock ECK, n number of internal addresses IAD including an external address EAD are generated and, in synchronization with the PLL clock PCK, n bits of internal write data ITD are generated to be written into a RAM macro 12. Thereafter, the external address EAD is latched, n number of the internal addresses IAD including the external address EAD are generated in synchronization with the PLL clock PCK, n bits of internal read data ITQ corresponding to n number of the internal addresses IAD are read from the RAM macro 12 in synchronization with the PLL clock PCK and the internal read data ITQ corresponding to the internal address IAD which coincides with a latch address LAD among n number of the internal addresses IAD is outputted.

Abstract: A technique is disclosed that can decrease a dynamic random access memory (DRAM) write access time to a selected memory cell while preventing destruction of write data to a non-selected memory cell connected to the same word line. After a sense amplifier (5j+1) has amplified a potential difference between non-selected bit lines (BLj+1 and /BLj+1), a write buffer (8) can drive selected bit lines (BLj and /BLj) according to write data for a selected memory cell (MCij). After a write buffer (8) has started to drive selected bit lines (BLj and /BLj), a sense amplifier (5j) can start to amplify the potential difference between such selected bit lines (BLj and /BLj).

Abstract: A plurality of address transition detecting circuits incorporated in a semiconductor memory device monitors address bits to see whether or not at least one address bits is changed in logic level for producing an address transition signal from the output signals of the respective address transition detecting circuits, and a plurality of charging transistors coupled in parallel between a power voltage line and a decoding line are respectively gated by the output signals of the address transition detecting circuits for charging the decoding line so that a decoding circuit quickly determines whether or not the stored address is matched with the address represented by the address bits for replacing a defective row of regular memory cells with a row of redundant memory cells.