Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5?1, 5?2, and 5?3 connected thereto not to overlap on the layout, the analog lines 5?1 and 5?2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5?1 and 5?2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5?1 and 5?2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5?1 and 5?2 can be suppressed. In another aspect, a semiconductor integrated circuit with a CMOS structure includes an analog circuit and a feedback loop, wherein an analog signal line for the feedback loop is wired outside a layout of the analog circuit.

Abstract: An integrated circuit includes CMOS circuit blocks and analog control lines arranged outside a layout of the CMOS circuit blocks so that the analog wiring and circuit blocks do not overlap each other. The distance of signal lines within a circuit block and the analog control lines can become as long as necessary, and the signal line within the circuit block and the analog control lines are not coupled via parasitic capacitance, and mutual interference is suppressed. In another aspect, a method of arranging a semiconductor integrated circuit includes providing a plurality of functional circuit blocks and connecting analog control wiring to the functional circuit blocks. The analog control wiring is arranged outside a layout of the functional circuit blocks on the semiconductor integrated circuit so that the analog control wiring does not overlap any one of the functional circuit blocks so as to reduce or eliminate interference between signal lines within a circuit block and the analog control lines.

Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5?1, 5?2, and 5?3 connected thereto not to overlap on the layout, the analog lines 5?1 and 5?2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5?1 and 5?2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5?1 and 5?2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5?1 and 5?2 can be suppressed. In another aspect, a semiconductor integrated circuit with a CMOS structure includes an analog circuit and a feedback loop, wherein an analog signal line for the feedback loop is wired outside a layout of the analog circuit.

Abstract: An integrated circuit includes CMOS circuit blocks and analog control lines arranged outside a layout of the CMOS circuit blocks so that the analog wiring and circuit blocks do not overlap each other. The distance of signal lines within a circuit block and the analog control lines can become as long as necessary, and the signal line within the circuit block and the analog control lines are not coupled via parasitic capacitance, and mutual interference is suppressed. In another aspect, a method of arranging a semiconductor integrated circuit includes providing a plurality of functional circuit blocks and connecting analog control wiring to the functional circuit blocks. The analog control wiring is arranged outside a layout of the functional circuit blocks on the semiconductor integrated circuit so that the analog control wiring does not overlap any one of the functional circuit blocks so as to reduce or eliminate interference between signal lines within a circuit block and the analog control lines.

Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5-1, 5-2, and 5-3 connected thereto not to overlap on the layout, the analog lines 5-1 and 5-2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5-1 and 5-2 can be suppressed.

Abstract: A plurality of decoding circuits 1a to 1f are arranged near a plurality of circuit blocks 2 to 7, which are arranged on the semiconductor chip 10 in a scattered manner, and the signal lines 8 prior to decoding, including the address lines and the data lines, are wired to each decoding circuit 1a to 1f. Through these wirings, the number of wirings routed over on the semiconductor chip 10 can be made in accordance with the number of bits of the signal lines 8 alone. So, compared with the past where the signal lines 20, which were great in number after decoding, were routed over to each circuit block 2 to 7, the wiring area as a whole can be greatly reduced. This can lead to miniaturization of chip size, reduction of crosstalk noise, and facilitation of layout.

Abstract: A radio receiver includes a noise canceller (2) for removing a pulse noise from a composite signal from an FM detection circuit (1), a stereo demodulation circuit (3) for demodulating the output signal of the noise canceller (2) to reproduce a stereo signal, and a VCO (21) for outputting a clock signal as an origin of a clock signal used in the stereo demodulation circuit (3). A clock signal used in a CCD (15) of the noise canceller (2) is generated based on a clock signal output from the VCO (21), so as to synchronize the phase of the signal used in the CCD (15) with the phase of the clock signal used in the stereo demodulation circuit (3), thereby suppressing generation of a beat signal in the output of the stereo demodulation circuit (3).

Abstract: An initial-stage amplifier 1 that deals with microsignals and other amplifiers 2 and 3 separate a power source line, and both separated power source lines 4 and 8 are commonly connected to a power source pad 6. This enables avoidance of the occurrence of a large potential difference between the initial-stage amplifier 1 and other amplifiers 2 and 3 due to differences in currents pulled to the amplifiers 1 to 3, and can prevent the occurrence of noise arising from such potential difference. Also, feedback loops are differentiated by the initial-stage amplifier 1 and other amplifiers 2 and 3. This can also prevent unfavorable effects where a large signal would be fed back from the rear-stage amplifiers 2 and 3 to the initial-stage amplifier 1.

Abstract: An IC chip 10 is divided into the analog circuit area 1 and a digital circuit area 2 in its layout. A clock generator circuit 6 that generates a clock signal CK is arranged within the digital circuit area 2, and a switching circuit 4 that performs switching operations by the clock signal CK is also arranged within the digital circuit area 2. This enables shortening of the wiring length of the clock line 9, which is routed from the clock generator circuit 6 to the switching circuit 4, and also enables the distance between the clock line 9 and the analog circuits within the analog circuit area 1 to be as great as possible. Through this, inconvenience where digital noise caused by the clock signal flowing through the clock line 9 jumps into analog circuits can be suppressed.

Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5-1, 5-2, and 5-3 connected thereto not to overlap on the layout, the analog lines 5-1 and 5-2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5-1 and 5-2 can be suppressed.

Abstract: An initial-stage amplifier 1 that deals with microsignals and other amplifiers 2 and 3 separate a power source line, and both separated power source lines 4 and 8 are commonly connected to a power source pad 6. This enables avoidance of the occurrence of a large potential difference between the initial-stage amplifier 1 and other amplifiers 2 and 3 due to differences in currents pulled to the amplifiers 1 to 3, and can prevent the occurrence of noise arising from such potential difference. Also, feedback loops are differentiated by the initial-stage amplifier 1 and other amplifiers 2 and 3. This can also prevent unfavorable effects where a large signal would be fed back from the rear-stage amplifiers 2 and 3 to the initial-stage amplifier 1.

Abstract: An IC chip 10 is divided into the analog circuit area 1 and a digital circuit area 2 in its layout. A clock generator circuit 6 that generates a clock signal CK is arranged within the digital circuit area 2, and a switching circuit 4 that performs switching operations by the clock signal CK is also arranged within the digital circuit area 2. This enables shortening of the wiring length of the clock line 9, which is routed from the clock generator circuit 6 to the switching circuit 4, and also enables the distance between the clock line 9 and the analog circuits within the analog circuit area 1 to be as great as possible. Through this, inconvenience where digital noise caused by the clock signal flowing through the clock line 9 jumps into analog circuits can be suppressed.