Abstract: A semiconductor device, having an input terminal configured to receive a multi-valued input signal as input, the multi-valued input signal including a plurality of values, a multi-valued logic circuit that operates with a multi-valued function and output binary signals to an output section in response to the input signal that has been input to the input terminal, the output section having a number of nodes being one less than a number of the plurality of values of the multi-valued input signal, and an impedance control circuit that is connected to the input terminal and the output section, and changes a combined resistance value in response to the binary signals of the plurality of nodes to change a current which flows in the input terminal.

Abstract: A semiconductor device, having a test circuit of a multivalued logic circuit without newly provision of an output terminal for a test signal, and with no increase in transmission delay in an output signal, includes an n-valued input terminal, and comparators that operate at different threshold voltages in response to input signals which have been input to the n-valued input terminal, respectively, and also includes an impedance control circuit that is connected to the n-valued input terminal and outputs of the comparators, respectively, and changes a combine resistance value in response to the output signals of the comparators to change a current flowing in the n-valued input terminal.

Abstract: A semiconductor device, having a test circuit of a multivalued logic circuit without newly provision of an output terminal for a test signal, and with no increase in transmission delay in an output signal, includes an n-valued input terminal, and comparators that operate at different threshold voltages in response to input signals which have been input to the n-valued input terminal, respectively, and also includes an impedance control circuit that is connected to the n-valued input terminal and outputs of the comparators, respectively, and changes a combine resistance value in response to the output signals of the comparators to change a current flowing in the n-valued input terminal.

Abstract: A dual-port SRAM operates for read and write operations in a single clock cycle. The SRAM has a comparator for comparing the read address and the write address to detect a coincidence therebetween. A bypass circuit bypasses the write data as a read data upon detection of a coincidence, whereas a timing circuit delays the write control signal with respect to the read control signal upon detection of no coincidence. The timing control between the read operation and the write operation reduces signal interference between the write data and the read data and enables a higher speed operation of the computer system.