Abstract: The present invention discloses a scan test circuit capable of dealing with the cases of various numbers of pins without being restricted by the number of scan pins of a semiconductor integrated circuit tester, and a semiconductor integrated circuit including the scan test circuit. When the number of scan chains within the chip of an LSI to be tested is n, the number of scan inputs given from the outside of the LSI is m, and the number of scan outputs output to the outside of the LSI is p, this scan test circuit is equipped with a scan input conversion circuit which carries out bit number conversion of m→n, and a scan output conversion circuit which carries out bit number conversion of n→p.

Abstract: In multiplying an absolute value of a high frequency component of an input video signal and a gain selected from an aperture compensation gain and a noise cancel gain to carry out the aperture compensation and the noise cancel of the video signal, upper or lower bits of the absolute value are selected dependent on a control selected from the aperture compensation and the noise cancel in accordance with a level of the absolute value and a level of the input video signal. In carrying out the addition and the subtraction between the input video signal and a multiplied value, upper or lower bits of the multiplied value are selected in the same manner as in the above multiplying stage. As a result, a scale of a multiplier can be small.

Abstract: In a digital video signal compensation circuit, a high frequency component of a digital video signal is obtained in a high-pass filter, and the high frequency component is compared in a comparator with a threshold signal, thereby determining whether the high frequency component is an edge component or a noise component. Where the high frequency component is the edge component, the high frequency component is added in an adder to the digital video signal, and where the high frequency component is a noise component, the high frequency component is subtracted in the adder from the digital video signal in accordance with the sign conversion of the high frequency component. Therefore, only one adder is provided in the digital video signal compensation circuit. That is, it is not necessary that an adder and a subtracter are provided therein.