Abstract: A unit selector (120) selects a predetermined number of power storage units from a plurality of power storage units (110) and connects the selected power storage units to an input/output terminal (140). A control unit (130) controls the unit selector (120). Specifically, during continuous discharge from the input/output terminal (140), the control unit (130) switches the power storage units (110) selected by the unit selector (120), and repeatedly selects the same power storage units (110) at intervals of time.

Abstract: Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

Abstract: Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.

Abstract: An interface circuit, which uses electromagnetic induction to perform a signal transmission, comprises a transmission coil and a transmission circuit that provides a signal to the transmission coil, thereby causing the transmission coil to output a triangular or roughly triangular magnetic field signal.

Abstract: A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values: Veye/?{square root over (3)}?Vref—H?Veye/?{square root over (2)}??(1) ?Veye/?{square root over (2)}?Vref—L??Veye/?{square root over (3)}??(2) More particularly, effect becomes remarkable by setting the reference potentials Vref_H and Vref_L to central values in ranges shown in Equations (1) and (2), respectively. In the central values, fluctuation (jitter) of transition data becomes the smallest, and a jitter characteristic of a reproducing clock becomes the best. Consequently, a clock reproducing apparatus in which a received clock from duobinary transmission data is reproduced with high accuracy is provide.

Abstract: There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.

Abstract: Precoded data transmitted from transmitting apparatus (101) is received by receiving apparatus (102) as duobinary data being ternary data via transmission path (103), and the duobinary data is converted into differential data being binary data by absolute value converter (121) comprising an AND gate and an OR gate.

Abstract: A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values: Veye/?{square root over (3)}?Vref—H?Veye/?{square root over (2)}??(1) ?Veye/?{square root over (2)}?Vref—L??Veye/?{square root over (3)}??(2) More particularly, effect becomes remarkable by setting the reference potentials Vref_H and Vref_L to central values in ranges shown in Equations (1) and (2), respectively. In the central values, fluctuation (jitter) of transition data becomes the smallest, and a jitter characteristic of a reproducing clock becomes the best. Consequently, a clock reproducing apparatus in which a received clock from duobinary transmission data is reproduced with high accuracy is provide.

Abstract: There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.

Abstract: A semiconductor device is provided with a plurality of semiconductor chips and at least one transmission coil (108) for transmitting signals by using inductor coupling between the semiconductor chips. A plurality of transmission coils are connected in series.

Abstract: A data receiving device comprises amplifying circuit 41 that amplifies received duobinary data with a given gain into an output signal, offset canceler 56, 57 that cancel an offset of the output signal from amplifying circuit 41, data determiner 43, 44 that sample the output signal from amplifying circuit 41 based on a first reference voltage and a second reference voltage which is of a lower level than the first reference voltage to determine which one of three levels of the duobinary data the received duobinary data have.

Abstract: An interface circuit, which uses electromagnetic induction to perform a signal transmission, comprises a transmission coil and a transmission circuit that provides a signal to the transmission coil, thereby causing the transmission coil to output a triangular or roughly triangular magnetic field signal.

Abstract: Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.

Abstract: Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.