Patents by Inventor Munetaka Masaki

Munetaka Masaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bias voltage applying circuit and semiconductor memory device
    Patent number: 7088626
    Abstract: Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: August 8, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumichi Mori, Takahiko Yoshimoto, Masahiko Watanabe, Shinsuke Anzai, Takeshi Nojima, Munetaka Masaki
  • Bias voltage applying circuit and semiconductor memory device
    Publication number: 20050174859
    Abstract: Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 11, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumichi Mori, Takahiko Yoshimoto, Masahiko Watanabe, Shinsuke Anzai, Takeshi Nojima, Munetaka Masaki