Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode.

Abstract: A semiconductor memory device includes a first circuit which generates a first potential lower than the external power supply voltage, a second circuit which generates a second potential lower than the first potential, a capacitor charged to the first potential, a bit line connected to a memory cell, a sense amplifier which performs sense operation to amplify a potential on the bit line to the second potential, and a connection control circuit which connects the first circuit to the sense amplifier within a first time period from a start of the sense operation, and which connects the second circuit to the sense amplifier after the lapse of the first time period. The first circuit is enabled before the start of the sense operation and is disabled after the completion of charging of the capacitor, and the output of the first circuit is thereby set in a floating state.