Patents by Inventor Muneyuki IMAI

Muneyuki IMAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404427
    Abstract: A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by t
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 2, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Muneyuki Imai, Junpei Kanazawa
  • Publication number: 20210391345
    Abstract: A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by t
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Yoshitaka OTSU, Muneyuki IMAI, Junpei KANAZAWA
  • Patent number: 11037943
    Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Muneyuki Imai, James Kai
  • Patent number: 10923358
    Abstract: In a substrate processing method for etching a silicon oxide layer formed on a surface of a substrate, a surface of the silicon oxide layer is hydrophilized. Then, the silicon oxide layer is etched by supplying a halogen-containing gas to the substrate and sublimating a reaction product generated by reaction between the halogen-containing gas and the silicon oxide layer.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Muneyuki Imai, Akitaka Shimizu
  • Publication number: 20190267391
    Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Muneyuki IMAI, James KAI
  • Publication number: 20190109012
    Abstract: In a substrate processing method for etching a silicon oxide layer formed on a surface of a substrate, a surface of the silicon oxide layer is hydrophilized. Then, the silicon oxide layer is etched by supplying a halogen-containing gas to the substrate and sublimating a reaction product generated by reaction between the halogen-containing gas and the silicon oxide layer.
    Type: Application
    Filed: February 17, 2017
    Publication date: April 11, 2019
    Inventors: Muneyuki IMAI, Akitaka SHIMIZU
  • Patent number: 10256107
    Abstract: There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Muneyuki Imai, Satoshi Toda
  • Patent number: 10141195
    Abstract: There is provided a substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, the method including: depositing a carbon-based deposit on the surface of the substrate; removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which a silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and removing the deposited carbon-based deposit.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Muneyuki Imai, Noriyuki Kobayashi
  • Publication number: 20180061657
    Abstract: There is provided a substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, the method including: depositing a carbon-based deposit on the surface of the substrate; removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which a silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and removing the deposited carbon-based deposit.
    Type: Application
    Filed: August 23, 2017
    Publication date: March 1, 2018
    Inventors: Muneyuki IMAI, Noriyuki KOBAYASHI
  • Publication number: 20170243753
    Abstract: There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 24, 2017
    Inventors: Muneyuki IMAI, Satoshi TODA