Abstract: A semiconductor device according to an embodiment includes a plurality of conductive layers stacked apart from each other and extending in a plate shape in a direction crossing a stacking direction; a channel body including a semiconductor film and penetrating the plurality of conductive layers; a memory film including a charge accumulation film and provided between the plurality of conductive layers and the channel body; and a high dielectric constant (high-k) film arranged between the plurality of conductive layers and the memory film while being divided in a circumferential direction surrounding the memory film.

Abstract: According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.

Abstract: A semiconductor device according to an embodiment includes a plurality of conductive layers stacked apart from each other and extending in a plate shape in a direction crossing a stacking direction; a channel body including a semiconductor film and penetrating the plurality of conductive layers; a memory film including a charge accumulation film and provided between the plurality of conductive layers and the channel body; and a high dielectric constant (high-k) film arranged between the plurality of conductive layers and the memory film while being divided in a circumferential direction surrounding the memory film.

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

Abstract: A semiconductor memory device includes: a plurality of conductive layers; a plurality of insulating layers; a semiconductor layer; and a plurality of electric charge accumulating layers. A conductive layer of the plurality of conductive layers has a first width at a first position where a surface opposed to the semiconductor layer is disposed and has a second width at a second position farther from an electric charge accumulating layer of the plurality of electric charge accumulating layers than the first position. The first width is smaller than the second width, a third width as a maximum width in the electric charge accumulating layer is equal to the first width or smaller than the first width, and the surface at the first position of the conductive layer has no portion that approaches the electric charge accumulating layer from a center to both ends.

Abstract: According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of conductive layers, a semiconductor layer, and charge accumulating sections; and a control circuit that executes an erase operation. The erase operation includes an erase mode that executes a first erase flow. The first erase flow includes: a first write operation in which a first program voltage is applied to the plurality of conductive layers; a first erase operation that is executed after the first write operation, and in which, while a first voltage is applied to a first conductive layer, a voltage higher than the first voltage is applied to the second conductive layer; and a second erase operation that is executed after the first erase operation, and in which, while the first voltage is applied to a second conductive layer, a voltage higher than the first voltage is applied to the first conductive layer.

Abstract: A semiconductor memory device comprises: a memory cell array comprising a plurality of conductive layers, a semiconductor layer, and charge accumulating sections; and a control circuit that executes an erase operation. The plurality of conductive layers include: one or a plurality not adjacent in a first direction, of first conductive layers; and one or a plurality not adjacent in the first direction, of second conductive layers different from the first conductive layers. The erase operation includes an erase mode that executes a first erase flow.

Abstract: A distance measurement system includes: a camera that captures an object; a robot that moves the camera or the object; and a control unit that controls the robot. The control unit includes: an operation control unit that operates the robot so that the camera or the object is located in a rectilinearly moved state between two different image-capturing positions at which a prescribed position on the object in the image obtained by the camera is located at the center of the image; a size calculating unit that calculates sizes of the object in the images obtained by the camera at the two image-capturing positions; and a distance calculating unit that calculates a distance from the camera to the object on the basis of the sizes of the object at the two image-capturing positions, calculated by the size calculating unit, and the distance between the two image-capturing positions.

Abstract: According to an embodiment, a semiconductor memory device includes a pillar member, a plurality of insulating layers arranged on an outer peripheral surface of the pillar member, an electrode film arranged between the insulating layers adjacent in a height direction, and a second block insulating film arranged between the electrode film and the pillar member and between the electrode film and the insulating layers. The pillar member includes a first block insulating film, a memory film, and a channel semiconductor layer in order from a side at its outer peripheral surface. The first block insulating film and the second block insulating film are made of an insulating material having a relative dielectric constant larger than that of silicon oxide. A distance between the memory film and the electrode film is a sum of a thickness of the first block insulating film and a thickness of the second block insulating film.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: A surface area of a transverse cross section of an upper portion of a columnar portion is greater than a surface area of a transverse cross section of a lower portion of the columnar portion. A configuration of the transverse cross section of the upper portion is a triangle or a pseudo-triangle having three corners, or a quadrilateral or a pseudo-quadrilateral having four corners. A configuration of the transverse cross section of the lower portion is substantially a circle. The upper portion of the columnar portion is adjacent to an upper layer portion of a stacked body including a control gate of an uppermost layer of control gates. The lower portion of the columnar portion is adjacent to a lower layer portion of the stacked body including a control gate of a lowermost layer of the control gates.

Abstract: A manufacturing management device includes first cell planning device connected to the manufacturing machine of first manufacturing cell, and second cell planning device connected to the manufacturing machine of second manufacturing cell. The planning part of the first cell planning device calculates quantity of operation that would be left unfinished with respect to the quantity stipulated in a manufacturing plan. The first cell planning device transmits a request for transfer including information on the quantity of operation that would be left unfinished to the second cell planning device. The second cell planning device modifies at least one of the operation period and the period of maintenance work of the manufacturing machine in the second manufacturing cell so as to increase the quantity of operation during the predetermined period.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: A surface area of a transverse cross section of an upper portion of a columnar portion is greater than a surface area of a transverse cross section of a lower portion of the columnar portion. A configuration of the transverse cross section of the upper portion is a triangle or a pseudo-triangle having three corners, or a quadrilateral or a pseudo-quadrilateral having four corners. A configuration of the transverse cross section of the lower portion is substantially a circle. The upper portion of the columnar portion is adjacent to an upper layer portion of a stacked body including a control gate of an uppermost layer of control gates. The lower portion of the columnar portion is adjacent to a lower layer portion of the stacked body including a control gate of a lowermost layer of the control gates.

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of charge accumulation type memory cells; and a control unit that controls the memory cell array. The control unit, when executing an erase operation on the memory cell array, applies an erase voltage to the memory cells. The erase voltage is a voltage in a pulse form. The control unit performs control that, compared to when the erase operation is in a first stage, increases a voltage value and shortens a pulse width of the erase voltage when the erase operation is in a second stage.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of memory cells, each of the memory cells including a tunneling insulating film provided on a substrate including silicon, a floating gate provided on the tunneling insulating film, an inter-gate insulating film provided on the floating gate, and a control gate provided on the inter-gate insulating film; and an element separation trench provided between the plurality of memory cells, the element separation trench having a gap in an interior of the element separation trench. The inter-gate insulating film is provided also above the element separation trench. An upper end of the gap is provided in an interior of the inter-gate insulating film provided above the element separation trench.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of memory cells, each of the memory cells including a tunneling insulating film provided on a substrate including silicon, a floating gate provided on the tunneling insulating film, an inter-gate insulating film provided on the floating gate, and a control gate provided on the inter-gate insulating film; and an element separation trench provided between the plurality of memory cells, the element separation trench having a gap in an interior of the element separation trench. The inter-gate insulating film is provided also above the element separation trench. An upper end of the gap is provided in an interior of the inter-gate insulating film provided above the element separation trench.