Patents by Inventor Munio ISHIMURA

Munio ISHIMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of manufacturing semiconductor device
    Patent number: 9601507
    Abstract: According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating layer, a spacer film provided in a side wall of the opening in a stepped shape, and configured to have an etching resistance lower than that of the insulating layer, and a conductive body provided in the opening to be configured to cover the spacer film.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Munio Ishimura
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20160276262
    Abstract: According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating layer, a spacer film provided in a side wall of the opening in a stepped shape, and configured to have an etching resistance lower than that of the insulating layer, and a conductive body provided in the opening to be configured to cover the spacer film.
    Type: Application
    Filed: July 16, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Munio ISHIMURA
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20160268291
    Abstract: According to one embodiment, a stacked body of N layers is stacked on a semiconductor substrate, steps are provided in the stacked body such that upper layers are retracted behind lower layers, N lower openings are provided in correspondence with the individual layers of the stacked body and are equal in depth, one to N upper openings are provided on one to N lower openings and are different in depth, N lower-layer contact electrodes are provided in the lower openings, and one to N upper-layer contact electrodes are provided in the upper openings.
    Type: Application
    Filed: August 3, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Munio ISHIMURA