Patents by Inventor Munir D. Naeem
Munir D. Naeem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8772850Abstract: A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.Type: GrantFiled: April 18, 2013Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
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Publication number: 20130228840Abstract: A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Applicant: International Business Machines CorporationInventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
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Patent number: 8492821Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.Type: GrantFiled: March 30, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Byeong Y. Kim, Munir D. Naeem, James P. Norum
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Patent number: 8426268Abstract: The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.Type: GrantFiled: February 2, 2010Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
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Publication number: 20120187465Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Byeong Y. Kim, Munir D. Naeem, James P. Norum
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Patent number: 8227311Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.Type: GrantFiled: October 7, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Byeong Y. Kim, Munir D. Naeem, James P. Norum
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Publication number: 20120086064Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Byeong Y. Kim, Munir D. Naeem, James P. Norum
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Patent number: 8003488Abstract: A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.Type: GrantFiled: September 26, 2007Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Munir D. Naeem, David M. Dobuzinsky, Byeong Y. Kim
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Patent number: 7871893Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.Type: GrantFiled: January 28, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
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Publication number: 20100193852Abstract: The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.Type: ApplicationFiled: February 2, 2010Publication date: August 5, 2010Applicant: International Business Machines CorporationInventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
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Patent number: 7592245Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.Type: GrantFiled: January 15, 2008Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Byeong Y. Kim, Effendi Leobandung, Munir D. Naeem, Brian L. Tessier
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Publication number: 20090189242Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
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Publication number: 20090104776Abstract: A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Dobuzinsky, Johnathan E. Faltermeier, Naoyoshi Kusaba, Joyce C. Liu, Munir D. Naeem, Siddhartha Panda, Richard S. Wise, Hongwen Yan
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Publication number: 20090079027Abstract: A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Munir D. Naeem, David M. Dobuzinsky, Byeong Y. Kim
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Publication number: 20090047791Abstract: A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Dobuzinsky, Johnathan E. Faltermeier, Munir D. Naeem, William C. Wille, Richard S. Wise
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Publication number: 20080224255Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.Type: ApplicationFiled: April 29, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeong Y. Kim, Munir D. Naeem, Frank D. Tamweber, Xiaomeng Chen
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Publication number: 20080169528Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeong Y. Kim, Munir D. Naeem, Frank D. Tamweber, Xiaomeng Chen
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Patent number: 7393738Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.Type: GrantFiled: January 16, 2007Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Byeong Y Kim, Munir D. Naeem, Frank D. Tamweber, Xiaomeng Chen
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Patent number: 7358172Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.Type: GrantFiled: February 21, 2006Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Byeong Y. Kim, Effendi Leobandung, Munir D. Naeem, Brian L. Tessier
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Patent number: 6893938Abstract: A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.Type: GrantFiled: April 21, 2003Date of Patent: May 17, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Munir D. Naeem, Hiroyuki Akatsu, Byeong Kim, Rolf Weis, David Mark Dobuzinksy, Johnathan E. Faltermeier