Patents by Inventor Munir Naeem

Munir Naeem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111044
    Abstract: A system and method of threat detection using a pulsed polarimetric radar system using microwave range of frequencies in the electromagnetic spectrum. The system uses a radar principle to transmit and receive the scattered response from the target. A time pulsed upconverted frequency system is used to sample the target over a specified radio frequency (RF) bandwidth. The full 2-port scattering matrix (comprising all co and cross s-parameters) is captured using only one antenna with an OMT and delay lines, that represent the target. Several decompositions are used to describe the polarimetric signature of the target. The system uses polarimetric approaches to measure scattering properties of anomalous object concealed beneath clothing. The co-polarized and cross-polarized signals are analyzed to determine if a person is carrying an anomalous object beneath their clothing.
    Type: Application
    Filed: April 3, 2023
    Publication date: April 4, 2024
    Inventors: Munir Ahmad TARAR, Nevine DEMITRI, Reza MOUSAVI, Diogo DUTRA, Farhan NAEEM
  • Publication number: 20080113507
    Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
    Type: Application
    Filed: January 15, 2008
    Publication date: May 15, 2008
    Applicant: International Business Machines Corporation
    Inventors: David Dobuzinsky, Byeong Kim, Effendi Leobandung, Munir Naeem, Brian Tessier
  • Publication number: 20070196963
    Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Dobuzinsky, Byeong Kim, Effendi Leobandung, Munir Naeem, Brian Tessier
  • Publication number: 20050051839
    Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Inventors: Johnathan Faltermeier, Jeremy Stephens, David Dobuzinsky, Larry Clevenger, Munir Naeem, Chienfan Yu, Larry Nesbit, Rama Divakaruni, Michael Maldei
  • Patent number: 6821900
    Abstract: A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: November 23, 2004
    Assignees: Infineon Technologies AG, International Business Machines
    Inventors: Satish Athavale, Rajiv Ranade, Munir Naeem, Gangadhara Swami Mathad
  • Publication number: 20020094690
    Abstract: A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.
    Type: Application
    Filed: January 9, 2001
    Publication date: July 18, 2002
    Inventors: Satish Athavale, Rajive Ranade, Munir Naeem, Gangadhara Swami Mathad