Patents by Inventor Munir Nayfeh

Munir Nayfeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200052141
    Abstract: A multi-junction solar cell includes a plurality of photovoltaic cell layers that are electrically connected and stacked to define upper and lower subcells having at least one step difference therebetween that exposes portions of the lower subcell such that, responsive to incident illumination, a current density of the exposed portions of the lower subcell is greater than that of portions thereof having the upper subcell thereon. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 13, 2020
    Inventors: Sabina ABDUL HADI, Ammar Munir NAYFEH, Eugene A. FITZGERALD
  • Patent number: 8367769
    Abstract: Embodiments of the invention provide silicon-based nanoparticle composites, where the silicon nanoparticles are highly luminescent. Preferred embodiments of the invention are Si—O solid composite networks, e.g., glass, having a homogenous distribution of luminescent hydrogen terminated silicon nanoparticles in a homogenous distribution throughout the solid. Embodiments of the invention also provide fabrication processes for silicon-based silicon nanoparticle composites. A preferred method for forming a silicon-based nanoparticle composite disperses hydrogen terminated silicon nanoparticles and an inorganic precursor of an organosilicon gel in an aprotic solvent to form a sol. A catalyst is mixed into the sol. The sol is then permitted to dry into a gel of the silicon-based nanoparticle composite.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: February 5, 2013
    Assignee: NanoSi Advanced Technologies, Inc.
    Inventors: Abdullah Saleh Aldwayyan, Mohamad Saleh AlSalhi, Abdurahman Mohammed Aldukhail, Mansour S. Alhoshan, Muhammad Naziruddin Khan, Ghassan K. Al-Chaar, Munir Nayfeh
  • Patent number: 8143079
    Abstract: Multiple films of red-green-blue (RGB) luminescent silicon nanoparticles are integrated in a cascade configuration as a top coating in an ultraviolet/blue light emitting diode (LED) to convert it to a white LED. The configuration of RGB luminescent silicon nanoparticle films harnesses the short wavelength portion of the light emitted from the UV/blue LED while transmitting efficiently the longer wavelength portion. The configuration also reduces damaging heat and/or ultraviolet effects to both the device and to humans.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 27, 2012
    Assignee: Goeken Group Corp.
    Inventors: Carlo Scianna, Munir Nayfeh, Abdulrahman Al-Muhanna
  • Patent number: 8084788
    Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Judson Robert Holt, Abhishek Dube, Eric C. T. Harley, Shwu-Jen Jeng, Jeremy J Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
  • Publication number: 20110229995
    Abstract: Multiple films of red-green-blue (RGB) luminescent silicon nanoparticles are integrated in a cascade configuration as a top coating in an ultraviolet/blue light emitting diode (LED) to convert it to a white LED. The configuration of RGB luminescent silicon nanoparticle films harnesses the short wavelength portion of the light emitted from the UV/blue LED while transmitting efficiently the longer wavelength portion. The configuration also reduces damaging heat and/or ultraviolet effects to both the device and to humans.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 22, 2011
    Applicant: POLYBRITE INTERNATIONAL INC.
    Inventors: Carlo Scianna, Munir Nayfeh, Abdulrahman Al-Muhanna
  • Patent number: 7919381
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: April 5, 2011
    Assignees: Canon Kabushiki Kaisha, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Patent number: 7772078
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: August 10, 2010
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Publication number: 20100159678
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Application
    Filed: March 8, 2010
    Publication date: June 24, 2010
    Applicants: CANON KABUSHIKI KAISHA, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Publication number: 20100090288
    Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Judson R. Holt, Abhishek Dube, Eric C.T. Harley, Shwu-Jen Jeng, Jeremy J. Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
  • Publication number: 20090061604
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 5, 2009
    Applicants: CANON KABUSHIKI KAISHA, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Patent number: 7495313
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: February 24, 2009
    Assignees: Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Publication number: 20060213779
    Abstract: The invention provides a method for the formation of silicon nanoparticles, in sizes that fluoresce, by electrodeposition of silicon material onto a non-reactive (with HF) metal (e.g., platinum) surface from a solution of silicate and HF or HF/H2O2. In an embodiment of the invention, a positively biased substrate with a platinum surface is immersed in a solution of sodium metasilicate in HF/H2O2, a current is drawn and a coating of silicon nanoparticles is formed on the platinum surface.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 28, 2006
    Inventors: Munir Nayfeh, Laila Abuhassan
  • Publication number: 20050072679
    Abstract: In the invention, an electrochemical etching of crystalline germanium or a germanium alloy produces well-segregated chromatic clusters of nanoparticles. Distinct strong bands appear in the photoluminescence spectra under 350 nm excitation with the lowest peaks in wavelength identified to be at 430, 480, and 580 and 680-1100 nm. The material may be dispersed into a discrete set of luminescent nanoparticles of 1-3 nm in diameter, which may be prepared into colloids and reconstituted into films, crystals, etc.
    Type: Application
    Filed: May 19, 2004
    Publication date: April 7, 2005
    Inventors: Munir Nayfeh, Laila Abuhassan, Ammar Nayfeh, Yia-Chung Chang