Patents by Inventor Mun-Jun Kim
Mun-Jun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626476Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: GrantFiled: November 10, 2020Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-Heon Lee
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Publication number: 20210057518Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ha-young YI, Youn-seok CHOI, Young-min KO, Mun-jun KIM, Hong-gun KIM, Seung-Heon LEE
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Patent number: 10879345Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: GrantFiled: November 11, 2019Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
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Publication number: 20200083319Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: ApplicationFiled: November 11, 2019Publication date: March 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ha-young YI, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
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Patent number: 10490623Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: GrantFiled: December 21, 2018Date of Patent: November 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
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Publication number: 20190131386Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: ApplicationFiled: December 21, 2018Publication date: May 2, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ha-young YI, Youn-seok CHOI, Young-min KO, Mun-jun KIM, Hong-gun KIM, Seung-heon LEE
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Patent number: 10170541Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: GrantFiled: May 22, 2017Date of Patent: January 1, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
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Publication number: 20170345886Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.Type: ApplicationFiled: May 22, 2017Publication date: November 30, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Ha-young YI, Youn-seok CHOI, Young-min KO, Mun-jun KIM, Hong-gun KIM, Seung-heon LEE
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Patent number: 9627469Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.Type: GrantFiled: December 17, 2015Date of Patent: April 18, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-young Yi, Jun-won Lee, Byoung-deog Choi, Jong-myeong Lee, Mun-jun Kim, Hong-gun Kim
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Publication number: 20160343799Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.Type: ApplicationFiled: December 17, 2015Publication date: November 24, 2016Inventors: Ha-young Yi, Jun-won Lee, Byoung-deog Choi, Jong-myeong Lee, Mun-jun Kim, Hong-gun Kim
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Publication number: 20110037109Abstract: In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.Type: ApplicationFiled: October 22, 2010Publication date: February 17, 2011Inventors: Hong-Gun KIM, Ju-Seon GOO, Mun-Jun KIM, Yong-Soon CHOI, Sung-Tae KIM, Eun-Kyung BAEK
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Patent number: 7842569Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.Type: GrantFiled: December 29, 2006Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Gun Kim, Ju-Seon Goo, Mun-Jun Kim, Yong-Soon Choi, Sung-Tae Kim, Eun-Kyung Baek
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Publication number: 20100072569Abstract: In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids.Type: ApplicationFiled: September 25, 2009Publication date: March 25, 2010Applicant: Samsung Electronics, Co., Ltd.Inventors: Tae-Jong Han, Mun-Jun Kim, Deok-Young Jung, Eun-Kyung Baek, Ju-Seon Goo
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Publication number: 20080035984Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.Type: ApplicationFiled: December 29, 2006Publication date: February 14, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-Gun KIM, Ju-Seon GOO, Mun-Jun KIM, Yong-Soon CHOI, Sung-Tae KIM, Eun-Kyung BAEK
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Publication number: 20070020879Abstract: In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.Type: ApplicationFiled: July 12, 2006Publication date: January 25, 2007Inventors: Eun-Kyung Baek, Ju-Seon Goo, Mun-Jun Kim, Hong-Gun Kim, Kyu-Tae Na
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Publication number: 20060105525Abstract: A method for forming a non-volatile memory device is provided. According to the method, a device isolation layer defining an active region is formed on the device isolation layer. An upper surface of the device isolation layer is formed higher than a surface of the substrate to form a gap region surrounded by the upper portion of the device isolation layer. A tunnel insulation layer is formed on the active region, and a floating gate layer is formed on an entire surface of the substrate. The floating gate layer is reflowed by performing a hydrogen annealing to fill a gap region with the reflowed floating gate layer. The reflowed floating gate layer is planarized until the device isolation layer is exposed to form a floating gate pattern.Type: ApplicationFiled: November 15, 2005Publication date: May 18, 2006Inventors: Hong-Suk Kim, Hyun Park, Mun-Jun Kim, Chang-Seob Kim
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Publication number: 20050224983Abstract: A semiconductor structure includes a material layer on a substrate and to be patterned, an amorphous carbon layer on the material layer to be patterned, an N-free anti-reflective layer on the amorphous carbon layer, and a photoresist layer on the N-free anti-reflective layer. The N-free anti-reflective layer contains SiCXOYHZ as a main element. Related methods of patterning semiconductor structures also are provided.Type: ApplicationFiled: October 26, 2004Publication date: October 13, 2005Inventors: Won-jin Kim, Hyun Park, Chang-seob Kim, Mun-jun Kim, Hye-min Kim, Jin-gyun Kim