Patents by Inventor Munsefar Khaleque

Munsefar Khaleque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware mechanism to mitigate stalling of a processor core
    Patent number: 10740102
    Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 11, 2020
    Assignee: Oracle International Corporation
    Inventors: Munsefar Khaleque, Nathan Sheeley, Mark Greenberg, Matthew Smittle, Paul Jordan
  • HARDWARE MECHANISM TO MITIGATE STALLING OF A PROCESSOR CORE
    Publication number: 20180246720
    Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.
    Type: Application
    Filed: February 24, 2017
    Publication date: August 30, 2018
    Inventors: Munsefar Khaleque, Nathan Sheeley, Mark Greenberg, Matthew Smittle, Paul Jordan