Patents by Inventor Mun Seon JANG
Mun Seon JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240096437Abstract: A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.Type: ApplicationFiled: December 13, 2022Publication date: March 21, 2024Inventors: Jin Ho JEONG, Dae Suk KIM, Mun Seon JANG
-
Patent number: 11265022Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.Type: GrantFiled: December 2, 2020Date of Patent: March 1, 2022Assignee: SK hynix Inc.Inventors: Mun Seon Jang, Hoiju Chung, Tae Kyun Kim
-
Publication number: 20210083690Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.Type: ApplicationFiled: December 2, 2020Publication date: March 18, 2021Inventors: Mun Seon JANG, Hoiju CHUNG, Tae Kyun KIM
-
Patent number: 10379786Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.Type: GrantFiled: September 7, 2016Date of Patent: August 13, 2019Assignee: SK hynix Inc.Inventors: Mun Seon Jang, Saeng Hwan Kim, Chang Ki Baek, Jae Woong Yun
-
Patent number: 10024915Abstract: A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.Type: GrantFiled: September 16, 2016Date of Patent: July 17, 2018Assignee: SK hynix Inc.Inventors: Dong Hee Han, Saeng Hwan Kim, In Tae Kim, Byoung Chul Lee, Mun Seon Jang
-
Patent number: 10014073Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.Type: GrantFiled: December 7, 2016Date of Patent: July 3, 2018Assignee: SK hynix Inc.Inventors: Mun Seon Jang, Saeng Hwan Kim, In Tae Kim, Chang Ki Baek
-
Publication number: 20170372796Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.Type: ApplicationFiled: December 7, 2016Publication date: December 28, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, In Tae KIM, Chang Ki BAEK
-
Publication number: 20170337105Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.Type: ApplicationFiled: September 7, 2016Publication date: November 23, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, Chang Ki BAEK, Jae Woong YUN
-
Publication number: 20170336471Abstract: A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.Type: ApplicationFiled: September 16, 2016Publication date: November 23, 2017Inventors: Dong Hee HAN, Saeng Hwan KIM, In Tae KIM, Byoung Chul LEE, Mun Seon JANG
-
Publication number: 20170242754Abstract: Semiconductor device including an input and output line control circuit may be provided. The input/output line control circuit may include a write connection circuit configured to transmit data of a write local line pair based on a write control signal. The input/output line control circuit may include a connection circuit configured to transmit data received from the write connection circuit to a write segment line pair based on a switching signal. The input/output line control circuit may be configured to transmit data of the write local line pair to the write segment line pair, based on the switching signal and the write control signal.Type: ApplicationFiled: June 1, 2016Publication date: August 24, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, Bo Yeun KIM
-
Patent number: 9501123Abstract: A power-up circuit of a semiconductor apparatus includes a detection block configured to detect a first target level of an external voltage and activate a power-up signal; and a bias block configured to divide the external voltage according to a division ratio that is variable in response to the power-up signal, and output a bias voltage.Type: GrantFiled: March 25, 2014Date of Patent: November 22, 2016Assignee: SK hynix Inc.Inventor: Mun Seon Jang
-
Publication number: 20160285372Abstract: A power driving circuit including a voltage generation unit configured to generate a release control signal and an output voltage. The power driving circuit including a release controller configured to enable a release signal during an activation section of a flag signal in response to the release control signal. The power driving circuit including a pull-up driving unit configured to increase a level of the output voltage in response to the release control signal. The power driving circuit including a release driving unit configured to synchronize a level of the output voltage in response to the release signal.Type: ApplicationFiled: July 28, 2015Publication date: September 29, 2016Inventor: Mun Seon JANG
-
Patent number: 9154092Abstract: An amplification circuit of a semiconductor apparatus includes a first amplification unit configured to amplify a difference between an input voltage and a reference voltage and generate a preliminary amplification signal, a second amplification unit configured to secondarily amplify the preliminary amplification signal and generate an amplification signal, and a compensation unit configured to form an addition current path.Type: GrantFiled: December 9, 2013Date of Patent: October 6, 2015Assignee: SK Hynix Inc.Inventor: Mun Seon Jang
-
Publication number: 20150185796Abstract: A power-up circuit of a semiconductor apparatus includes a detection block configured to detect a first target level of an external voltage and activate a power-up signal; and a bias block configured to divide the external voltage according to a division ratio that is variable in response to the power-up signal, and output a bias voltage.Type: ApplicationFiled: March 25, 2014Publication date: July 2, 2015Applicant: SK hynix Inc.Inventor: Mun Seon JANG
-
Publication number: 20150061763Abstract: An amplification circuit of a semiconductor apparatus includes a first amplification unit configured to amplify a difference between an input voltage and a reference voltage and generate a preliminary amplification signal, a second amplification unit configured to secondarily amplify the preliminary amplification signal and generate an amplification signal, and a compensation unit configured to form an addition current path.Type: ApplicationFiled: December 9, 2013Publication date: March 5, 2015Applicant: SK hynix Inc.Inventor: Mun Seon JANG