Patents by Inventor Muntaquim F. Chowdhury

Muntaquim F. Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
    Patent number: 6687809
    Abstract: An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: February 3, 2004
    Assignee: Intel Corporation
    Inventors: Muntaquim F. Chowdhury, Douglas M. Carmean
  • Method and apparatus for maintaining processor ordering
    Publication number: 20030088760
    Abstract: According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data structure of a first processor. It is determined whether a load address of a first load instruction matches one of the store addresses in the first data structure. The first load instruction is replayed if the load address of the first load instruction matches one of the store addresses in the first data structure.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 8, 2003
    Inventors: Muntaquim F. Chowdhury, Douglas M. Carmean
  • Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
    Patent number: 6484254
    Abstract: According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data structure of a first processor. It is determined whether a load address of a first load instruction matches one of the store addresses in the first data structure. The first load instruction is replayed if the load address of the first load instruction matches one of the store addresses in the first data structure.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Intel Corporation
    Inventors: Muntaquim F. Chowdhury, Douglas M. Carmean
  • Write-combining device for uncacheable stores
    Patent number: 6334171
    Abstract: A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: December 25, 2001
    Assignee: Intel Corporation
    Inventors: Dave L. Hill, Douglas M. Carmean, Brent E. Lince, Muntaquim F. Chowdhury