Abstract: Methods, systems, and apparatus for near-store computing. The summarizer system includes a task controller. The task controller is configured to receive, from a host, a work item. The task controller is configured to determine a current workload of a storage controller on a solid state drive (SSD). The task controller is configured to determine a work strategy to utilize at least one of the host or the storage controller based on the current workload of the storage controller.

Abstract: An energy conservation module may be included in a mobile communication device that receives requests for services from application programs running in the device. For each request, the energy conservation module may determine which of different, selectable ways of performing the request is likely to be the most energy efficient. The energy conservation module may then cause the request to be performed in this most energy-efficient way. This determination may be dynamic and based on current operating conditions. Middleware between the application programs and an operating system may be included that presents various APIs to the application programs to allow them to easily invoke this functionality. The different, selectable ways of performing the services may be of any type, including different, selectable computer network interfaces (e.g., Wi-Fi and cellular) and whether a complex computation should be performed within or outside of the mobile communication device.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: An automated guardband compensation system automatically compensates for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit automatically and repeatedly requests: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.

Abstract: An energy conservation module may be included in a mobile communication device that receives requests for services from application programs running in the device. For each request, the energy conservation module may determine which of different, selectable ways of performing the request is likely to be the most energy efficient. The energy conservation module may then cause the request to be performed in this most energy-efficient way. This determination may be dynamic and based on current operating conditions. Middleware between the application programs and an operating system may be included that presents various APIs to the application programs to allow them to easily invoke this functionality. The different, selectable ways of performing the services may be of any type, including different, selectable computer network interfaces (e.g., Wi-Fi and cellular) and whether a complex computation should be performed within or outside of the mobile communication device.

Abstract: An automated guardband compensation system may automatically compensate for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit may automatically and repeatedly request: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: A device for determining the traffic conditions between measurement locations associated with a roadway is provided. The device includes a processor that is capable of determining when a specified measurement location is passed or traversed and measure data as well as start a time period. If a device is traveling towards another specified measurement location but does not reach the location before the time period expires, a new measurement update may be sent by the device to a server. The information in this update may be utilized by the server to determine that there is a slowdown or blockage in traffic and/or that there is a traffic jam between the measurement locations. The device is capable of receiving a traffic update(s) from the server which may specify traffic conditions between the measurement locations. The traffic conditions may indicate that there is a traffic slowdown/blockage between the measurement locations.

Abstract: A device for determining when a virtual trip line has been crossed or traversed is provided. The device includes a memory for storing the virtual trip lines which are defined pairs of location descriptors corresponding to a geographic area. The device further includes a processor that is capable of determining the location of the device when it crosses a virtual trip line as well as its speed and direction. The processing element is further capable of sending this information to another electronic device such as a server that may determine a number of vehicles crossing a virtual trip line for a specified amount of time, the average speed of vehicles crossing the virtual trip line and the traffic density in a region near the virtual trip line. The device is capable of receiving the information that was determined by the server.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A device for determining the traffic conditions between measurement locations associated with a roadway is provided. The device includes a processor that is capable of determining when a specified measurement location is passed or traversed and measure data as well as start a time period. If a device is traveling towards another specified measurement location but does not reach the location before the time period expires, a new measurement update may be sent by the device to a server. The information in this update may be utilized by the server to determine that there is a slowdown or blockage in traffic and/or that there is a traffic jam between the measurement locations. The device is capable of receiving a traffic update(s) from the server which may specify traffic conditions between the measurement locations. The traffic conditions may indicate that there is a traffic slowdown/blockage between the measurement locations.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A device for determining when a virtual trip line has been crossed or traversed is provided. The device includes a memory for storing the virtual trip lines which are defined pairs of location descriptors corresponding to a geographic area. The device further includes a processor that is capable of determining the location of the device when it crosses a virtual trip line as well as its speed and direction. The processing element is further capable of sending this information to another electronic device such as a server that may determine a number of vehicles crossing a virtual trip line for a specified amount of time, the average speed of vehicles crossing the virtual trip line and the traffic density in a region near the virtual trip line. The device is capable of receiving the information that was determined by the server.

Abstract: Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.

Abstract: Methods and apparatus to transfer data from a stacked memory are described. In one embodiment, an interconnect may be utilized to transfer data into a buffer from one or more opened memory pages.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.