Abstract: A method and apparatus for enabling individual cells in a Cell Matrix to detect when they have been configured to act as a simple wire, and to bypass their internal logic accordingly. Such bypass conditions result in faster data transmission from input to output. When sets of adjacent cells are each configured to act as a wire, significantly faster transmission of data through the cells can be achieved by this bypass routing. Also disclosed is a means for selectively disconnecting unused inputs from internal logic, thereby further increasing switching speed across cells utilizing this bypass routing.

Abstract: A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of each device is specified by a small program memory contained inside each device. Any device's program memory can be read or written by any other device connected to it within the array. This facilitates the development of extremely parallel systems whose configuration can be modified at runtime, while distributing control of the array throughout the entire array itself. The resulting system is thus completely self-reconfigurable, avoiding the bottlenecks and critical failure points found in inherently externally-configured systems.