Abstract: A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

Abstract: A design method for implementing a high-memory algorithm for motion estimation and compensation uses a low internal memory processor and a DMA engine that interacts with the processor and the algorithm. The DMA takes care of large data transfers from an external memory to the processor internal memory and vice-versa, without using the CPU clock cycles. The design method is scalable and is suited to handle huge bandwidths without slowing down the processor. To prevent the processor from being idle during DMA, the processing is pipelined and staggered so that motion compensation is performed on an earlier block or data that is available, while DMA fetches the reference data for the current block. Several DMAs may be set up under an ISR if necessary. The invention has application in video decoders including those conforming to H.264, VC-1, and MPEG-4 ASP.

Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.

Abstract: Efficient techniques are provided to detect and correct channel errors found in an encoded video signal. In one example embodiment, header information in a video frame is analyzed to detect channel errors in the video frame. The video frame is then corrected for detected channel errors by isolating the detected channel errors to a few macroblocks in the video frame to reduce data loss and improve video quality.