Patents by Inventor Murali Ramadoss

Murali Ramadoss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410311
    Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Kritika Bala, Murali Ramadoss, Hema Nalluri, Jeffery Boles, Jeffrey Frizzell, Joseph Koston
  • Publication number: 20190259127
    Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: January 2, 2019
    Publication date: August 22, 2019
    Inventors: Abhishek Venkatesh, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Publication number: 20190251740
    Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.
    Type: Application
    Filed: December 11, 2018
    Publication date: August 15, 2019
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu
  • Publication number: 20190244418
    Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 8, 2019
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle
  • Publication number: 20190227801
    Abstract: An apparatus and method for scalable interrupt reporting.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 25, 2019
    Inventors: RAJESH SANKARAN, ANKUR SHAH, BRYAN WHITE, HEMA NALLURI, DAVID PUFFER, MURALI RAMADOSS, ALTUG KOKER, ADITYA NAVALE, BALAJI VEMBU
  • Publication number: 20190215769
    Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 11, 2019
    Applicant: Intel Corporation
    Inventors: Eric C. Samson, Murali Ramadoss, Marc Beuchat
  • Publication number: 20190204901
    Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.
    Type: Application
    Filed: December 21, 2018
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Marc Beuchat
  • Publication number: 20190197657
    Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Altug Koker, Ingo Wald, David Puffer, Subramaniam M. Maiyuran, Prasoonkumar Surti, Balaji Vembu, Guei-Yuan Lueh, Murali Ramadoss, Abhishek R. Appu, Joydeep Ray
  • Patent number: 10332302
    Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 25, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Publication number: 20190180494
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 28, 2018
    Publication date: June 13, 2019
    Inventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
  • Patent number: 10303902
    Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Hema C. Nalluri, Aditya Navale, Murali Ramadoss
  • Patent number: 10282812
    Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Altug Koker, Ingo Wald, David Puffer, Subramaniam M. Maiyuran, Prasoonkumar Surti, Balaji Vembu, Guei-Yuan Lueh, Murali Ramadoss, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20190130635
    Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
  • Patent number: 10261570
    Abstract: The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Sathyanarayanan Srinivasan
  • Patent number: 10242494
    Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramanian Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle
  • Publication number: 20190087983
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 21, 2019
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Patent number: 10235736
    Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, Subramaniam M. Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, James A. Valerio, Eric J. Hoekstra, Arthur D. Hunter, Jr.
  • Patent number: 10210655
    Abstract: By scheduling/managing workload submission to a position only shading pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. An interface submits workloads to a slave engine running in one parallel pipe to assist a main engine running in another parallel pipe. Command sequences for each parallel pipe are separated to enable the slave engine to run ahead of the main engine. The slave engine is a position only shader and the main engine is a render engine.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
  • Patent number: 10204394
    Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Patent number: 10191759
    Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: David J. Cowperthwaite, Murali Ramadoss, Ankur N. Shah, Balaji Vembu, Altug Koker, Aditya Navale