Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics eng

Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for provisioning virtualized tile-based graphics processing circuitry. For example, one embodiment of an apparatus comprises: processing resources to process commands including graphics commands and generate results; resource partitioning circuitry to partition the processing resources into a plurality of tiles in accordance with a specified tile-based resource allocation policy; and graphics virtualization circuitry to perform tile-based allocation of the processing resources to a plurality of virtual machines in accordance with a specified virtualization policy, the virtual machines to be executed in a virtualized execution environment.

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a graphics processor comprising a compute unit to execute multiple concurrent threads and a memory coupled with and on a same package as the compute unit. The memory can store thread state for a suspended thread and the compute unit can detect that multiple concurrent threads of the compute unit are blocked from execution. Upon detection, the compute unit can select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and select an additional thread to be executed. The compute unit can then replace the victim thread with an additional thread to be executed. The additional thread to be executed can be based on a blocking event for the additional thread.

Abstract: Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.