Abstract: In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an 110 device page table.

Abstract: In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

Abstract: Conversion of an array of structures (AOS) to a structure of arrays (SOA) improves the efficiency of transfer from the AOS to the SOA. A similar technique can be used to convert efficiently from an SOA to an AOS. The controller performing the conversion computes a partition size as the highest common factor between the structure size of structures in AOS and the number of banks in a first memory device, and transfers data based on the partition size, rather than on the structure size. The controller can read a partition size number of elements from multiple different structures to ensure that full data transfer bandwidth is used for each transfer.

Abstract: In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Abstract: Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

Abstract: Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

Abstract: Reaching a determination associated with a class of an object is disclosed. An identifier associated with the class of the object is extracted from a pointer to the object. The extracted identifier is compared to a comparison value. At least in part using a result of the comparison a determination is reached.

Abstract: Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

Abstract: Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

Abstract: A multi-mode texture compression algorithm is provided for effective compression and decompression texture data during graphics processing. Initially, a request is sent to memory for compressed texture data. Such compressed texture data is then received from the memory in response to the request. At least one of a plurality of compression algorithms associated with the compressed texture data is subsequently identified. Thereafter, the compressed texture data is decompressed in accordance with the identified compression algorithm.

Abstract: A system and method for compressing and decompressing a texture image that: (1) compresses each texel to 8 bits, and when decompressed, each texel is of a quality comparable to a 256 color palettized image; (2) increases the efficiency of the decompression system and method by eliminating complex operations, e.g., multiplication; and (3) increases the efficiency of the system and method when switching between textures that use different palettes, when compared to conventional system and methods. The invention compresses a texture image, stores the compressed texture image, and quickly and efficiently decompresses the texture image when determining a value of a pixel. The texture image compression technique utilizes a palletized color space that more closely matches the colors in the texture image while allocating an unequal number of bits to the color channels.

Abstract: A system and method for automatically selecting a color space for use in compressing and decompressing a texture image that automatically determines a compression color space for each texture image. The invention selects a compression color space manually, or preferable, using a neural network algorithm. The invention initializes the neural network that includes an input layer of neurons and a hidden layer of neurons. Each input layer neuron has an associated weight that is equal to the combination of the weights of a Y neuron, an A neuron, and a B neuron that is associated with each input layer neuron. The texel image is reduced into a representative sample of colors and input vectors from the texel image are randomly selected. For each input vector, the invention determines the two input layer neurons that most closely match the input vector and modifies the weights of the two input layer neurons to more closely match the value of the input vector.