Abstract: In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAS.

Abstract: A method allows two substantially asynchronous system components of a logic emulation system to exchange data packets with reference to a clock signal of predetermined frequency. In one example, each bit is transmitted across the system components over two or more cycles of the clock signal. The reference clock signal can be distributed to the two system components from a common clock signal generator, or can be generated locally independently.

Abstract: In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAs.

Abstract: A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ("sample signals") are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.