Patents by Inventor Muralidhar Ramachandran

Muralidhar Ramachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having localized extremely thin silicon on insulator channel region
    Patent number: 8685847
    Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: April 1, 2014
    Assignees: International Business Machines Corporation, Advanced Micro Devices Corporation, Freescale Semiconductor Corporation
    Inventors: Amlan Majumdar, Robert J. Miller, Muralidhar Ramachandran
  • Semiconductor device having localized extremely thin silicon on insulator channel region
    Publication number: 20120104498
    Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR CORPORATION, ADVANCED MICRO DEVICES CORPORATION
    Inventors: Amlan Majumdar, Robert J. Miller, Muralidhar Ramachandran