Abstract: An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

Abstract: A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.

Abstract: A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.

Abstract: An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

Abstract: A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

Abstract: A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.

Abstract: An operational amplifier including at least one amplifier stage and chopping circuitry for chopping an input signal to the amplifier stage and an output signal from the chopping signal having a frequency randomly varying within the selected frequency band.

Abstract: A multiple-stage operational amplifier including a gain stage for amplifying an input signal and implementing a dominant pole producing a frequency response having a gain roll-off with frequency and a unity gain frequency. An intermediate stage is coupled to an output of the gain stage and has a high input impedance and a low output impedance. A high gain amplifier configured as a low gain output stage using resistive feedback and coupled to an output of the intermediate stage drives an output of the operational amplifier and implements a dominant pole at a frequency substantially higher than the unity gain frequency implemented by the dominant pole implemented the gain stage.

Abstract: An operational amplifier including at least one amplifier stage and chopping circuitry for chopping an input signal to the amplifier stage and an output signal from the chopping signal having a frequency randomly varying within the selected frequency band.

Abstract: A method of testing an integrated circuit including the steps of observing a selected parameter at a selected test mode to detect an error. The current to the integrated circuit is stepped from a reference level by selected amount.

Abstract: A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

Abstract: A method of testing an internal block of an integrated circuit includes testing an internal block under a selected operating condition by setting a selected operating parameter to a value emulating operation of the internal block under another operating condition to detect potential failure of the internal block under the another operating condition.

Abstract: An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.

Abstract: Disclosed in this application is the placement of an additional integrator between the first stage integrator output and the input to the attenuator/low pass filter. This approach reduces the input referred offset by a factor equal to the gain of the additional integrator, and the offset of the additional integrator itself will be divided by the gain of the first-stage integrator.

Abstract: Disclosed is a chopper-stabilized amplifier with current steering used as output switching and to be operated in a low power supply voltage environment.