Abstract: A radio receiver is arranged to detect a symbol boundary in a received encoded signal, by receiving the signal, and correlating a portion of the received signal against a predetermined training field sequence to generate a correlation signal. The portion of the received signal has a length which is shorter than the length of the predetermined training field sequence. The radio receiver is also arranged to compare the correlation signal to a threshold derived from the received signal, and identify at least one peak in the correlation signal if any portion of the correlation signal exceeds the threshold. The symbol boundary is derived from the at least one peak.

Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. The algorithm is implemented in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. The soft Reed-Solomon (RS) decoding scheme extracts candidate RS symbols and their Log Likelihood Ratios (LLRs) from QAM symbols. The set of highest probable candidate blocks are then chosen and these are decoded using a variant of the Chase algorithm until a valid codeword is detected at the decoder output.

Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.