Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

Abstract: Higher write speeds in hard disk write preamplifiers require higher supply voltages. The voltage across an inductive write head, VL, is proportional to the value of inductance, L, and to the speed at which the write current is reversed, di/dt. Accordingly, the write current reversal time in inductive write-heads fundamentally depends on how large a voltage can be impressed across the write drive head. The proposed circuitry and method provides a voltage boost circuit for hard disk drive preamplifiers that satisfies the demand for improved rise-time while meeting the conflicting demand for maintaining a same supply voltage.

Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

Abstract: A hard disk drive write channel architecture improves the rise-time while utilizing a same supply voltage to provide a boosted voltage, thereby improving the rise-time only when it is needed. The voltage is then connected to the inductive write head through a switch after an appropriate delay, so as to compensate for the delay between the switching of Data line and the peaking of the voltage at the corresponding write terminal. In addition, the same delayed version of the Data line is applied to the inputs of the switching circuit to delay the signal inputs such that the delay timing matches appropriately.