Abstract: A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.

Abstract: A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells; and computing data characterizing a relationship between a variability of delay and a magnitude of delay shared among the cells in the family of cells.

Abstract: Methods, systems, and devices for designing and/or analyzing of integrated circuits are disclosed.

Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

Abstract: A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.

Abstract: A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.