Patents by Inventor Murong Lang

Murong Lang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127481
    Abstract: A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a first threshold level to determine whether a first condition is satisfied. The value is also compared to a second threshold level to determine whether a second condition is satisfied. In response to satisfying the first condition, a read scrub operation associated with the memory sub-system is executed. In response to satisfying the second condition, a write scrub operation associated with the memory sub-system is executed.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Zhongguang Xu, Zhenming Zhou
  • Patent number: 11107543
    Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Murong Lang
  • Publication number: 20210225442
    Abstract: A method is disclosed that includes causing a first set of a plurality of voltage pulses to be applied to memory cells of a memory device, a voltage pulse of the first set of the voltage pulses placing the memory cells of the memory device at a voltage level associated with a defined voltage state. The method also includes determining a set of bit error rates associated with the memory cells of the memory device in view of a data mapping pattern for the memory cells of the memory device, wherein the data mapping pattern assigns a voltage level associated with a reset state to at least a portion of the memory cells of the memory device. The method further includes determining whether to apply one or more second sets of the voltage pulses to the memory cells of the memory device in view of a comparison between the set of bit error rates for the memory cells and a previously measured set of bit error rates for the memory cells.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Publication number: 20210132867
    Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slope value represents a change of a read voltage level as a function of a delay time of a memory sub-system. Using the data structure, a stored slope value corresponding to a measured die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value. The read command is executed using the adjusted read voltage level.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 6, 2021
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 10971228
    Abstract: A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Publication number: 20210065824
    Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 4, 2021
    Inventors: Zhenming Zhou, Murong Lang
  • Publication number: 20210065790
    Abstract: A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Publication number: 20210064277
    Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 10908845
    Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slop value represents a change of a read voltage level as a function of a write-to-read delay time of a memory sub-system. In response to a read command, a current write-to-read delay time and a current die temperature are determined. Using the data structure, a stored slope value corresponding to the current die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value and the current write-to-read delay time. The read command is executed using the adjusted read voltage level.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: February 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 10910069
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Publication number: 20200321060
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 10790036
    Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. A plurality of test demarcation voltages is determined based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell. For each test demarcation voltage, an error rate of reading the state of the memory cell based on a respective test demarcation voltage is determined. A test demarcation voltage having the lowest error rate from the plurality of test demarcation voltages is determined. The current demarcation voltage is set to correspond to the test demarcation voltage having the lowest error rate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Murong Lang
  • Patent number: 10726925
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Publication number: 20200098434
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 9852800
    Abstract: Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: December 26, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Murong Lang, Deepanshu Dutta, Cynthia Hsu
  • Publication number: 20170256320
    Abstract: Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 7, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Murong Lang, Deepanshu Dutta, Cynthia Hsu