Patents by Inventor Murong Lang
Murong Lang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250251864Abstract: Aspects of the present disclosure configure a memory sub-system controller to perform a low-stress refresh erase (LSRE) in response to NAND detect empty page (NDEP) operations. The controller performs a first type of erase operation on a portion of a set of memory components. The controller performs a set of memory operations for detecting an empty page in the portion of the set of memory components. The controller, in response to determining that the set of memory operations for detecting the empty page in the portion of the set of memory components has failed, performs a second type of erase operation on the portion of the set of memory components.Type: ApplicationFiled: February 5, 2025Publication date: August 7, 2025Inventors: Murong Lang, Lei Lin, Guang Hu, Zhongguang Xu, Hanping Chen, Zhenming Zhou, Ronit Roneel Prakash
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Patent number: 12379864Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.Type: GrantFiled: March 26, 2024Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Peng Zhang, Murong Lang, Christina Papagianni, Zhenming Zhou
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Publication number: 20250224880Abstract: Methods, systems, and devices for techniques for memory cell degradation protection are described. In some cases, a memory system may perform a protection operation on blocks of memory cells in response to monitoring the temperature of the memory system. For example, the memory system may monitor the temperature associated with the system over a duration. If the temperature exceeds a threshold, a counter may be adjusted by a first value. If the counter exceeds a second threshold, the memory system may trigger one or more protection operations on the blocks of memory cells. These protection operations may include programming a data pattern to each block of memory cells.Type: ApplicationFiled: January 6, 2025Publication date: July 10, 2025Inventors: Zhongguang Xu, Peng Zhang, Murong Lang
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Patent number: 12354684Abstract: A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.Type: GrantFiled: January 20, 2022Date of Patent: July 8, 2025Assignee: Micron Technology, Inc.Inventors: Jian Huang, Zhenming Zhou, Murong Lang, Zhongguang Xu, Jiangli Zhu
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Publication number: 20250210125Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value by measuring a voltage at a select gate of a block while applying a maximum voltage to a drain select line, responsive to determining that the parameter value satisfies a threshold criterion, concluding that the select gate of the block is defective, and responsive to receiving an enhanced erase command referencing the block, discarding the enhanced erase command.Type: ApplicationFiled: March 10, 2025Publication date: June 26, 2025Inventors: Zhongguang Xu, Zhenlei Shen, Murong Lang
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Publication number: 20250210115Abstract: A processing device in a memory sub-system performs a read disturb scan on a block of a memory device to detect that a read disturb scan has been triggered for a partial block of the memory device. The processing device initiates one or more programmed wordline scans of the one or more wordlines having associated memory cells that have been programmed. Responsive to the one or more wordlines having associated memory cells that have been programmed passing the one or more programmed wordline scans, the processing device initiates an unprogrammed wordline scan of the one or more wordlines having associated memory cells that are empty. Responsive to the one or more wordlines having associated memory cells that are empty failing the one or more unprogrammed wordline scans, the processing device marks the partial block as closed to prevent additional programming of the partial block.Type: ApplicationFiled: December 19, 2024Publication date: June 26, 2025Inventors: Peng Zhang, Zhongguang Xu, Murong Lang, Zhenming Zhou
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Publication number: 20250201326Abstract: A sacrificial block in a die of a plurality of dies of a memory device is identified. Responsive to performing a data retention test on the sacrificial block, a threshold voltage shift of at least one logical programming level of the sacrificial block is identified. A block family error avoidance data structure is generated for the die of the plurality of dies comprising a plurality of read level offsets based on the threshold voltage shift.Type: ApplicationFiled: December 3, 2024Publication date: June 19, 2025Inventors: Murong Lang, Zhongguang Xu, Li-Te Chang
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Publication number: 20250138996Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.Type: ApplicationFiled: October 25, 2023Publication date: May 1, 2025Inventors: Li-Te Chang, Charles S. Kwong, Wei Wang, Murong Lang, Shenming Zhou
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Publication number: 20250140320Abstract: Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.Type: ApplicationFiled: July 25, 2024Publication date: May 1, 2025Inventors: Hanping Chen, Zhongguang Xu, Murong Lang, Zhenming Zhou
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Publication number: 20250118364Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.Type: ApplicationFiled: December 19, 2024Publication date: April 10, 2025Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Tingjun Xie, Jiangli Zhu, Nagendra Prasad Ganesh Rao, Sead Zildzic
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Patent number: 12272418Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.Type: GrantFiled: September 6, 2023Date of Patent: April 8, 2025Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Zhenlei Shen, Murong Lang
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Publication number: 20250111886Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Li-Te Chang, Murong Lang, Zhenming Zhou, Ting Luo
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Publication number: 20250104772Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Inventors: Tingjun Xie, Murong Lang, Fangfang Zhu, Jiangli Zhu, Zhenming Zhou
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Patent number: 12260916Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: GrantFiled: January 4, 2024Date of Patent: March 25, 2025Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
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Patent number: 12242755Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.Type: GrantFiled: February 6, 2024Date of Patent: March 4, 2025Assignee: Micron Technology, Inc.Inventors: Zhenming Zhou, Murong Lang, Ching-Huang Lu, Nagendra Prasad Ganesh Rao
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Publication number: 20250069675Abstract: The disclosure configures a memory sub-system controller to use prior read verify operations to selectively apply enhancements to read window budgets (RWB). The controller receives a request to perform a memory operation on data stored in an individual memory component of a set of memory components. The controller accesses RWB tracking information associated with the individual memory component and determines that the tracking information associated with the individual memory component indicates a need for enhancing a RWB associated with the memory operation. The controller applies one or more enhancement processes to the individual memory component in response to determining that the tracking information associated with the individual memory component indicates the need for enhancing the RWB associated with the memory operation.Type: ApplicationFiled: July 16, 2024Publication date: February 27, 2025Inventors: Daniel Zhang, Yu-Chung Lien, Peng Zhang, Murong Lang, Zhenming Zhou
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Publication number: 20250061928Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu, Jiangli Zhu
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Patent number: 12216529Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.Type: GrantFiled: September 19, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Jian Huang, Zhenming Zhou, Zhongguang Xu, Murong Lang
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Patent number: 12217794Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.Type: GrantFiled: January 29, 2024Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Tingjun Xie, Jiangli Zhu, Nagendra Prasad Ganesh Rao, Sead Zildzic
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Publication number: 20250036307Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.Type: ApplicationFiled: October 10, 2024Publication date: January 30, 2025Inventors: Murong Lang, Christina Papagianni, Zhenming Zhou, Ting Luo