Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.

Abstract: A predicted parallel branch slicer for use in an adaptive decision feedback equalizer includes Mk adders commonly receiving a signal to be processed and respectively receiving Mk preset values, and performing respective addition operations to generate Mk output signals; Mk slicers in communication with the Mk adders, receiving and processing the Mk output signals to obtain Mk signals of Mk levels, respectively; a multiplexer in communication with the Mk slicers, receiving the signals of the Mk levels; and k delay units interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mk levels to be outputted.

Abstract: In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A controller embeds a volatile memory, a plurality of application circuits and an arbiter. Each of the application circuits is capable of sending a request signal to request access the volatile memory and has a unique priority. When some of the application circuits send requests in a same period, the arbiter selects application circuits with higher priority among those application circuits such that the selected application circuits are allowed to access the volatile memory. The arbiter includes a plurality of arbiter modules and a main arbiter module. Each of the arbiter modules is assigned to a unique set of application circuits in the controller such that the arbiter modules can select higher priority application circuits in the corresponding sets at the same time. The main arbiter module further selects application circuits for accessing the volatile memory according to application circuits selected by the arbiter modules.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A predicted parallel branch slicer for use in an adaptive decision feedback equalizer includes Mk adders commonly receiving a signal to be processed and respectively receiving Mk preset values, and performing respective addition operations to generate Mk output signals; Mk slicers in communication with the Mk adders, receiving and processing the Mk output signals to obtain Mk signals of Mk levels, respectively; a multiplexer in communication with the Mk slicers, receiving the signals of the Mk levels; and k delay units interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mk levels to be outputted.

Abstract: A network switch chip and a method for controlling the same are proposed. A first network switch chip is cascaded with a second network switch chip. Each of the network switch chip comprises a high-speed network port and a plurality of connection ports. The two network switch chips are connected through the two high-speed network ports to form a direct link therebetween, and the network switch provides a transmission rate equal to the sum of transmission rates of the first connection ports and the second connection ports. The two network switch chips can update an operation status for each other through the direct link and whereby the first network switch chip and the second network switch can manage data exchange therebetween. Each of the network switch chips has a lookup table therein and the network switch chips can update the lookup table for each other.

Abstract: A controller embeds a volatile memory, a plurality of application circuits and an arbiter. Each of the application circuits is capable of sending a request signal to request access the volatile memory and has a unique priority. When some of the application circuits send requests in a same period, the arbiter selects application circuits with higher priority among those application circuits such that the selected application circuits are allowed to access the volatile memory. The arbiter includes a plurality of arbiter modules and a main arbiter module. Each of the arbiter modules is assigned to a unique set of application circuits in the controller such that the arbiter modules can select higher priority application circuits in the corresponding sets at the same time. The main arbiter module further selects application circuits for accessing the volatile memory according to application circuits selected by the arbiter modules.

Abstract: A test platform device for testing an embedded memory of a system on chip includes a first socket, a second socket and a test control circuit. The first socket is used for plugging therein the system on chip to be tested. The second socket is used for plugging therein an independent memory chip. The test control circuit is electrically connected to the first socket and the second socket, performs a comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip and outputting an error data when incomparable results are obtained in response to the comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: This invention discloses a long-distance network transmission structure and associated device thereof. The invention utilizes the CAT-5 transmission line network to achieve a high-speed long-distance network tranceiving. A DSP PHY (Digital Signal Processing Physical) is employed in the long-distance network transmission structure to receive a data signal from the transmission line. The signal is then driven to clients with a common PHY without DSP capability or a DSP PHY. Through such a DSP PHY, the signal can be transmitted over 3000 ft and the transmission rate can reach duplex 100 Mbps. Two pairs of cords inside the CAT-5 network transmission line are used to provide the full duplex data tranceiving and the other two spare cords provide electrical power for a repeater. Therefore, the long-distance transmission structure and associated device thereof can effectively reduce the cost for both network service providers and clients and facilitate the installation.