Patents by Inventor Murray J. Robinson

Murray J. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10843465
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 24, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Publication number: 20190047289
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 14, 2019
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Patent number: 10124588
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 13, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Patent number: 9536112
    Abstract: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: January 3, 2017
    Assignees: STMicroelectronics Asia Pacific Pte Ltd., STMicroelectronics
    Inventors: TeckKhim Neo, Paul I. Mikulan, Murray J. Robinson, Rube M. Ross
  • Publication number: 20160107444
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 21, 2016
    Inventors: MURRAY J. ROBINSON, KENNETH J. STEWART
  • Patent number: 9308728
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 12, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Publication number: 20140354735
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Publication number: 20120317662
    Abstract: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 13, 2012
    Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS ASIA PACIFIC PTE LTD. (Singapore)
    Inventors: TeckKhim NEO, Paul I. MIKULAN, Murray J. ROBINSON, Rube M. ROSS
  • Patent number: 5536966
    Abstract: An improved Schottky transistor structure (6), including a bipolar transistor structure (7) and a Schottky diode structure (8), is formed by retrograde diffusing relatively fast diffusing atoms to form a localized retrograde diode well (9) as the substrate for the Schottky diode structure. An expanded buried collector layer (11) formed of relatively slow diffusing atoms underlies the base and collector regions of the bipolar transistor structure (7) and the retrograde diode well (9). A diode junction (10) is formed by expanding the base contact of the bipolar transistor structure to include the surface of the retrograde diode well. Preferably, the diode junction is a Platinum-Silicide junction.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: July 16, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Christopher C. Joyce, Timwah Luk
  • Patent number: 5326710
    Abstract: A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL.
    Type: Grant
    Filed: September 10, 1992
    Date of Patent: July 5, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Christopher C. Joyce, Murray J. Robinson
  • Patent number: 5268316
    Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: December 7, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Christopher C. Joyce, Tim Wah Luk
  • Patent number: 5150177
    Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: September 22, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Christopher C. Joyce, Tim W. Luk
  • Patent number: 5075254
    Abstract: A slotted metallic die attach pad is disclosed for attachment of a semiconductor die, such as a silicon die, to form a die assembly demonstrating significantly reduced die attach stress. A plurality of substantially parallel, unidirectional slots in the die attach pad permits deformation of the die attach pad at the slots to compensate for differences in the thermal expansion coefficients of the silicon die and the metallic die attach pad. Stress sensitive components of the die are aligned in a stress sensitive direction, and the die is bonded on the die attach pad so that the stress sensitive direction is generally orthongonal to the longitudinal axes of the slots. A method for relieving die stress in a die assembly is also disclosed.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: December 24, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Ywan-Lung Tsay
  • Patent number: 4952999
    Abstract: A slotted metallic die attach pad is disclosed for attachment of a semiconductor die, such as a silicon die, to form a die assembly demonstrating significantly reduced die attach stress. A plurality of substantially parallel, unidirectional slots in the die attach pad permits deformation of the die attach pad at the slots to compensate for differences in the thermal expansion coefficients of the silicon die and the metallic die attach pad. Stress sensitive components of the die are aligned in a stress sensitive direction, and the die is bonded on the die attach pad so that the stress sensitive direction is generally orthogonal to the longitudinal axes of the slots. A method for relieving die stress in a die assembly is also disclosed.
    Type: Grant
    Filed: April 26, 1988
    Date of Patent: August 28, 1990
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Ywan-Lung Tsay