Abstract: A digitally programmable hysteresis comparator a includes digitally programmable variable resistor. One or more control bits are operable to modify the resistance of the variable resistor, and such modification is operable to modify the hysteresis width of the comparator.

Abstract: A liquid crystal display (LCD) bias generator generates a plurality of bias voltages, e.g., four bias voltages, needed to drive a segmented LCD. The LCD bias generator has a voltage generator, e.g., charge pump, that may generate a most positive voltage, e.g., substantially equal to or more positive than VDD, on the integrated circuit that may also be used for maintaining proper reverse bias operation of well ties and analog switches of the integrated circuit. Other necessary LCD bias voltages, e.g., three voltages, may also be derived from the LCD bias generator to provide bias and contrast control voltages required by the LCD. Having a more positive bias voltage than the power supply voltage, VDD, allows VDD to cover a wider range of voltages, e.g., powered from a battery, by eliminating the need for complex analog switch and pad designs for the integrated circuit.

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.