Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.

Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.