Abstract: A memory array comprises a plurality of rows and a plurality of columns, each row comprising at least one addressable word. The memory array comprises at least one redundant row and at least one redundant column. Error detection circuitry analyzes the memory array by addressing words and detecting errors within the addressed words. Error repair circuitry selects for a detected error either a redundant row or a redundant column to replace one of the row or column containing the error. It is determined for the detected error whether the error is a single error bit in the addressed word or whether it is one of a plurality of error bits within the word. If the error is the latter, then the error repair circuitry preferentially selects a redundant row rather than a redundant column to repair the error.

Abstract: The apparatus comprises derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different from other derived addresses in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses and is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value.

Abstract: A memory array comprising a plurality of rows and a plurality of columns, each row comprising at least one addressable word, said memory array comprising at least one redundant row and at least one redundant column; error detection circuitry for analysing said memory array, by addressing words within said memory array and detecting errors within said addressed words; error repair circuitry for selecting for a detected error either a redundant row or a redundant column to replace one of said row or column containing said error; wherein said error repair circuitry is configured to determine for said detected error whether said error is a single error bit in said addressed word or whether it is one of a plurality of error bits within said word, and if said error is said one of said plurality of errors, said error repair circuitry is configured to preferentially select a redundant row rather than a redundant column to repair said error.

Abstract: An apparatus and method are provided for performing a test sequence to detect address decoder open faults in a memory device. The apparatus comprises base address generation circuitry for generating a plurality of base addresses, and derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different to any other derived address in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses.