Abstract: One particular implementation conforming to aspects of the present disclosure takes the form of an input device for a computing system. The input device includes a input surface on which one or more input characters are shown and one or more sensors to detect which input character is pressed or selected by the user. In one example, the input device may include one or more piezo-electric sensors that detect an acoustic pulse created when the user taps on the input surface to indicate a selected input. Each character of the input surface of the input device creates a different acoustic pulse signature when tapped such that, upon detection and receiving of the acoustic pulse at the piezo-electric sensors, the input device or computer system may compare the received pulse to a database of stored pulse signatures to determine which character on the surface of the input device was tapped by the user.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value immediately preceding the corresponding element in the first list; and outputting the plurality of run values into a second vector register; where the above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to pack bit streams of variable lengths including: receiving a first bit segment from a first vector register; receiving a second bit segment from a second vector register; determining whether or not the sum of the bit length of the first bit segment and the bit length of the second bit segment is larger than a required length; generating a third bit segment from the first and second bit segments; and outputting the third bit segment in a third vector register; where the above operations are performed in response to the microprocessor receiving a first single instruction.

Abstract: Methods and apparatuses for decoding a compressed video stream. In one aspect of the invention, a method to decode a variable length encoded bit stream includes: concurrently processing first data obtained from variable length decoding a first code word in a register while variable length decoding a second code word in the register. In one example, processing the first data includes: looking up an inverse zigzag index; computing an Inverse Direct Cosine Transformation (IDCT) coefficient; storing the IDCT coefficient in a buffer in a transposed inverse zigzag order; and branching conditionally based on a condition encountered in variable length decoding the first code word.