Patents by Inventor Mussie T. Negussie

Mussie T. Negussie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176009
    Abstract: A method and apparatus for implementing power up detection in a power down cycle to dynamically determine whether a failed component in a system prevents another Initial Program Load (IPL) or re-IPL, or result in a loss of resources. Predefined mandatory functions are called to collect power down/up data that prevents re-IPL, or results in the reduction of resources. A user is notified, allowing the customer to continually utilize the system, while ordering hardware to be replaced.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lee N. Helgeson, Derek Howard, Russel L. Young, George J. Romano, Mussie T. Negussie
  • Patent number: 10997084
    Abstract: A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Edward Galbraith, Damir Anthony Jamsek, Andrew Kenneth Martin, Daniel Frank Moertl, Mussie T. Negussie, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis, Milos Stanisavljevic
  • Publication number: 20210064538
    Abstract: A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Robert Edward Galbraith, Damir Anthony Jamsek, Andrew Kenneth Martin, Daniel Frank Moertl, Mussie T. Negussie, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis, Milos Stanisavljevic
  • Patent number: 10901850
    Abstract: Examples of techniques for a thread checkpoint table for a computer processor are described herein. An aspect includes, based on detecting an early power-off warning (EPOW) signal, determine, based on a thread checkpoint table, whether a status of a thread of a processor indicates that the thread has begun a unit of atomic work. Another aspect includes, based on determining that the status of the thread of the processor indicates that the thread has begun the unit of atomic work, allowing the thread to continue execution of the unit of atomic work. Another aspect includes determining, based the status of the thread in the thread checkpoint table, that the thread has completed the unit of atomic work. Another aspect includes, based on determining that the thread has completed the unit of atomic work, suspending the thread.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert E. Galbraith, Dylan R. Gransee, Ethan J. Johnson, Austin J. Mackedanz, Mussie T. Negussie, Shannon C. Strutz
  • Publication number: 20200233475
    Abstract: Examples of techniques for a thread checkpoint table for a computer processor are described herein. An aspect includes, based on detecting an early power-off warning (EPOW) signal, determine, based on a thread checkpoint table, whether a status of a thread of a processor indicates that the thread has begun a unit of atomic work. Another aspect includes, based on determining that the status of the thread of the processor indicates that the thread has begun the unit of atomic work, allowing the thread to continue execution of the unit of atomic work. Another aspect includes determining, based the status of the thread in the thread checkpoint table, that the thread has completed the unit of atomic work. Another aspect includes, based on determining that the thread has completed the unit of atomic work, suspending the thread.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 23, 2020
    Inventors: Robert E. Galbraith, Dylan R. Gransee, Ethan J. Johnson, AUSTIN J. MACKEDANZ, Mussie T. Negussie, SHANNON C. STRUTZ
  • Publication number: 20200117562
    Abstract: A method and apparatus for implementing power up detection in a power down cycle to dynamically determine whether a failed component in a system prevents another Initial Program Load (IPL) or re-IPL, or result in a loss of resources. Predefined mandatory functions are called to collect power down/up data that prevents re-IPL, or results in the reduction of resources. A user is notified, allowing the customer to continually utilize the system, while ordering hardware to be replaced.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 16, 2020
    Inventors: Lee N. Helgeson, Derek Howard, Russel L. Young, George J. Romano, Mussie T. Negussie