Patents by Inventor Mustafa Amin

Mustafa Amin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220214951
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Applicant: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Patent number: 11378622
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: July 5, 2022
    Assignee: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Publication number: 20120295608
    Abstract: An apparatus, system, method and program detect and reduce interference in cell sites of a wireless communications network. A cell site from the cell sites of the wireless communications network is selected and signal code power measurements from mobile devices in the cell site are received so that the sources of signals being transmitted to the mobile devices can be determined. Interfering sources are determined based on the signal code power measurements and the active set of sources for the mobile devices. The signal code power measurements are summed and ranked, and interfering transmitters associated with the ranked signal code power measurements for the interfering sources are determined. The same procedure is repeated for all cell sites of the wireless communications network, and the transmitter that is an interfering source for the highest number of cell sites is selected as a problem (interfering) transmitter.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Inventors: Mustafa Amin Sahin, Osama Tarraf