Abstract: Methods and apparatus for performing machine learning tasks, and in particular, a hybrid architecture that includes both neural processing unit (NPU) and compute-in-memory (CIM) elements. One example neural-network-processing circuit generally includes a plurality of CIM processing elements (PEs), a plurality of neural processing unit (NPU) PEs, and a bus coupled to the plurality of CIM PEs and to the plurality of NPU PEs. One example method for neural network processing generally includes processing data in a neural-network-processing circuit comprising a plurality of CIM PEs, a plurality of NPU PEs, and a bus coupled to the plurality of CIM PEs and to the plurality of NPU PEs; and transferring the processed data between at least one of the plurality of CIM PEs and at least one of the plurality of NPU PEs via the bus.

Abstract: A die is described. The die includes a first seal ring on a periphery of the die, which encloses a core of the die. The die also includes one or more bridge interconnect structures across the first seal ring to route a signal from a test pad outside of the first seal ring to a circuit in the core.

Abstract: A package includes a first die, a second die, and a third die. The first die includes first active circuitry, and a first plurality of conductive vias (CVs) that has a first pitch. The second die includes second active circuitry proximate to a first side of the second die. The second active circuitry includes metal layers and a second plurality of CVs that extends from a second side of the second die to one or more of the metal layers. The second plurality of CVs has a second pitch greater than the first pitch. The third die includes a third plurality of CVs to electrically couple the second active circuitry to a substrate. The third plurality of CVs has a third pitch greater than the first pitch. The second die is disposed between the first die and the third die.

Abstract: A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.

Abstract: A stacked system-on-chip (SoC) is described. The stacked SoC comprises a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also comprises a compute logic die. The compute logic die comprises a static random-access memory (SRAM) comprising a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die comprises a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

Abstract: Disclosed are integrated circuit structures with buried rails and backside metals for routing input signals to and/or output signals from one or more cells of the integrated circuit structures. Port landing-free connections to input ports and/or from output ports are enabled. As a result, signal routing flexibility is enhanced.

Abstract: A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

Abstract: A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a base die having an array of processing units (PUs) including at least one spare PU. The 3D stacked memory package also includes memory dies stacked on the base die and having bank tiles, including at least one spare bank tile. The 3D stacked memory package further includes a package substrate supporting the base die. The 3D stacked memory package also includes through substrate vias (TSVs) extending between the memory dies and landing on the base die and having at least one spare TSV per bank tile. The 3D stacked memory package further includes a repair structure configured to reroute a data/control bus to replace one of a failed bank tile with the spare bank tile, a failed TSV with the at least one spare TSV, and/or a failed PU with the spare PU.

Abstract: A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a plurality of memory dies stacked on the base die. The 3D stacked memory package also includes a package substrate supporting the base die. The 3D stacked memory package further includes a plurality of processing units (PUs) arranged on the base die. The plurality of processing units are located at different locations of the base die. The 3D stacked memory package also includes one or more system buses on the base die and coupled between the one or more PUs and through silicon via (TSV) groups of the plurality of memory dies landing on the base die.

Abstract: A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having a memory cell array coupled to a wordline-bitline fanout structure. Additionally, the 3D memory structure includes a second memory die having peripheral logic formed from a second semiconductor substrate. A backside of the second memory die is hybrid bonded with a backside of the first memory die.

Abstract: A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.

Abstract: A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through hybrid bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.

Abstract: A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a base die. The 3D stacked memory package also includes memory dies stacked on the base die and including through silicon vias (TSVs) at a first pitch. The 3D stacked memory package also a compression-redistribution die between the memory dies and the base die. The compression-redistribution die includes second TSVs at a second pitch greater than the first pitch.

Abstract: A device comprising a memory device comprising a first memory chip comprising a first memory portion; and a first processor in memory portion, wherein the first processor in memory portion includes a first plurality of logic cells and at least one first capacitor; and a second memory chip coupled to the first memory chip.

Abstract: A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.

Abstract: A device comprising a substrate; and a stack of chips coupled to the substrate, wherein the stack of chips comprises: a logic chip; and a first memory chip coupled to the logic chip, wherein the first memory chip comprises a first die substrate; a first plurality of memory cells; and a first plurality of memory cell structures located along at least one edge of the first memory chip.

Abstract: A memory wafer is described. The memory wafer includes memory dies on the memory wafer. Additionally, the memory wafer includes wire connections at least partially within one of the memory dies. The wire connections are configured to couple to memory test and repair pads along at least one scribe line between the one of the memory dies and adjacent memory dies.

Abstract: Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.

Abstract: Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

Abstract: A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.