Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Abstract: A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.

Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Abstract: A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Energy function values are determined for bits of the codeword based on soft information for the bits of the codeword. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

Abstract: A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an Error Correction Code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.

Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

Abstract: A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region.