Abstract: A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

Abstract: A microprocessor instruction for performing an in-place byte swap on 32-bit data type to convert data stored in a big-endian memory format to a little-endian memory format, or visa-versa, is described. The invention comprises a modified barrel shifter which includes a plurality of multiplexers for selectively coupling data from one or more input buses to an output bus. The coupling of the individual bit lines of the data buses is arranged such that the lower order bits of the 32-bit quantity are exchanged with the higher order bits and visa-versa. Control lines connected to each of the multiplexers provide a means for controlling the byte swapping operation.

Abstract: A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed.

Abstract: A computer system includes a microprocessor having an internal cache memory and control unit that performs write-back operations to external memory responsive to an external signal indicating that a valid external address has been driven onto the address pins of the microprocessor. Under control of a state machine control, a unit within the microprocessor provides an indication signal to the external component that a current write cycle is a write-back cycle; this enables the system to distinguish between an ongoing write cycle generated by the processor, and a new write-back cycle. An additional signal is generated by the microprocessor in the event that the external address indicates a cache hit to a modified line.

Abstract: A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.

Abstract: A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to snooping and the remaining address ports provide concurrent access to the cache for references to one or more independent addresses respectively issued by one or more pipes. A tag port is provided for each of the address ports to provide concurrent hit/miss status for each address.

Abstract: A processor for processing information is described. The processor can select between a write-burst mode of transferring information and an individual write cycle mode of transferring information. The write-burst mode of transferring information is a transfer of information in a single burst transaction and the individual write cycle mode of transferring information is a transfer of information in separate write cycles.

Abstract: An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a bank selector for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath for transfering data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic for prioritizing the multiple data accesses when multiple data accesses are to be same bank.