Patents by Inventor Mustansir Hussainy Kheraluwala

Mustansir Hussainy Kheraluwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9178400
    Abstract: A cooling arrangement for a motor assembly includes a motor operably connected to a load. Also included is a motor controller disposed adjacent to, and fluidly coupled to, the motor, the motor controller disposed within a housing enclosing a cooling fluid for immersion of a plurality of motor controller components. Further included is a duct arrangement configured to route a cooling flow to a location proximate the housing of the motor controller for cooling therealong.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: November 3, 2015
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Debabrata Pal, Mustansir Hussainy Kheraluwala, Eric Alan Carter, Robert Scott Downing, Charles Patrick Shepard
  • Publication number: 20140232219
    Abstract: A cooling arrangement for a motor assembly includes a motor operably connected to a load. Also included is a motor controller disposed adjacent to, and fluidly coupled to, the motor, the motor controller disposed within a housing enclosing a cooling fluid for immersion of a plurality of motor controller components. Further included is a duct arrangement configured to route a cooling flow to a location proximate the housing of the motor controller for cooling therealong.
    Type: Application
    Filed: September 25, 2012
    Publication date: August 21, 2014
    Inventors: Debabrata Pal, Mustansir Hussainy Kheraluwala, Eric Alan Carter, Robert Scott Downing, Charles Patrick Shepard
  • Patent number: 6392365
    Abstract: A hot restrike protection circuit provides complete shut down protection for a self-oscillating high intensity discharge lamp ballast of the type comprising a pair of complementary switching devices in a bridge configuration with a gate drive inductor in series with a second inductor, i.e., a control inductor, at the junction between the switching devices. The hot restrike protection circuit effectively comprises a three-terminal device for coupling across the control inductor. In particular, the HRP circuit comprises a sensing network for sensing voltage across the control inductor, a breakdown network for providing a breakdown path upon reaching a predetermined restrike voltage threshold across the control inductor, and a shutdown network for shutting down operation of the ballast until the lamp is sufficiently cool for restarting, thereby protecting ballast components during hot restrike, or re-ignition, of the lamp.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: May 21, 2002
    Assignee: General Electric Company
    Inventors: Rui Zhou, Mustansir Hussainy Kheraluwala, Louis Robert Nerone, Weizhong Tang
  • Patent number: 6377461
    Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: April 23, 2002
    Assignee: General Electric Company
    Inventors: Burhan Ozmat, Mustansir Hussainy Kheraluwala, Eladio Clemente Delgado, Charles Steven Korman, Paul Alan McConnelee
  • Patent number: 6232151
    Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: May 15, 2001
    Assignee: General Electric Company
    Inventors: Burhan Ozmat, Mustansir Hussainy Kheraluwala, Eladio Clemente Delgado, Charles Steven Korman, Paul Alan McConnelee
  • Patent number: 5999424
    Abstract: A control method and apparatus for reducing transformer core volume in a power converter of the type having a switching circuit coupled to a primary winding of the transformer for selectively coupling the primary winding to a dc voltage source, a secondary winding of the transformer being coupled to an output rectifier circuit for developing a relatively high dc voltage across an output capacitor. The apparatus includes a high voltage zener diode clamp for limiting the maximum voltage on the capacitor, and the rectifier circuit includes at least a pair of zener diodes connected for blocking reverse current flow through the rectifier circuit.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: December 7, 1999
    Assignee: General Electric Company
    Inventors: Michael Joseph Schutten, Mustansir Hussainy Kheraluwala
  • Patent number: 5910709
    Abstract: A ballast system for at least one dimmable fluorescent lamp includes a resonant switching inverter and a controller which controls the inverter to operate above resonance during starting and normal running operation. After a start delay timer allows time for the lamp filaments to heat up, the controller provides control signals to a gate driver to drive the switching devices of the switching inverter initially at a relatively high frequency and then reduces the frequency until a sufficiently high voltage is reached to start the lamp. Once the lamp is started, the inverter is operated in its normal feedback mode. The ballast system further includes an overvoltage shutdown mechanism. During lamp starting, if either the output of the start delay timer is high or the output voltage is greater than a first overvoltage shutdown threshold, then an overvoltage shutdown timer is activated to shut down operation of the inverter for a predetermined overvoltage shutdown period.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: June 8, 1999
    Assignee: General Electric Company
    Inventors: Ljubisa Dragoljub Stevanovic, Robert Louis Steigerwald, Mustansir Hussainy Kheraluwala
  • Patent number: 5898583
    Abstract: A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: April 27, 1999
    Assignee: General Electric Company
    Inventors: Eladio Clemente Delgado, Mustansir Hussainy Kheraluwala
  • Patent number: 5892673
    Abstract: A high-density control circuit for an auxiliary resonant commutation pole (ARCP) circuit is internal to the ARCP package and includes a state machine sequencer for providing control and timing signals to achieve high-efficiency, zero-voltage, and fault-tolerant switching converter operation. The phase leg controller receives as inputs a phase enable signal and a pulse width modulation (PWM) signal from a system controller and gate drive feedback signals from main and auxiliary gate drivers. There are four paths the state machine sequencer can take when making a transition from one dc rail to the other, depending on whether the main diode or main switch is conducting and the magnitude and polarity of the inverter pole output current.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: April 6, 1999
    Assignee: General Electric Company
    Inventors: Eladio Clemente Delgado, Mustansir Hussainy Kheraluwala