Abstract: A circuit includes: an output terminal; a first transistor; and a clamp circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor coupled to the output terminal. The clamp circuit has a second transistor and a clamp controller. The second transistor has a first terminal, a second terminal, and a control terminal. The clamp controller has a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor is coupled to the control terminal of the first transistor. The third terminal of the clamp controller is coupled to the control terminal of the second transistor. The clamp controller includes a capacitor having a first terminal and a second terminal. The first terminal of the capacitor is coupled to the third terminal of the clamp controller.

Abstract: Described embodiments include a voltage clamping circuit having a threshold-setting circuit with a threshold input and a threshold output. A switch has a first terminal coupled to the threshold input, a second switch terminal, and a switch control terminal. A first transistor is coupled between the threshold output and the switch control terminal, and has a first control terminal. A second transistor is coupled between the first control terminal and ground, and has a second control terminal. A first driver circuit has a first driver input and a first driver output. A second driver circuit has a second driver input coupled to the first driver input, and a second driver output. A third transistor is coupled between the threshold input and ground, and has a third control terminal that is coupled to the second control terminal and the second switch terminal.

Abstract: Described embodiments include a gate drive circuit with a first transistor coupled between an input voltage terminal and a switching terminal, and having a first control terminal. A second transistor is coupled between the switching terminal and ground, and has a second control terminal. A first driver circuit has a first driver output coupled to the first control terminal, a first positive supply input coupled to a bootstrap voltage terminal, and a first negative supply input coupled to the switching terminal. A second driver circuit has a second driver output coupled to the second control terminal, a second positive supply input coupled to a driver supply, and a first negative supply input coupled to ground. An active clamp circuit is coupled between the driver supply and ground, and prevents a voltage between the driver supply and ground from exceeding a threshold voltage.

Abstract: The techniques and circuits, described herein, include solutions for latch-up prevention in multi-phase direct current (DC) to DC converters by ensuring safe pulse width modulation (PWM) control sequencing. In some aspects a latch-up pre-detection circuit has first and second detection inputs configured to receive high-side and low-side PWM signals respectively. The latch-up pre-detection circuit is configured to monitor for a transition from a first state to a second state based on the first and second detection inputs. The transition from the first state to the second state may be associated with condition(s) favorable for latch-up. Upon detecting the transition from the first state to the second state, the latch-up pre-detection circuit can output a pulse signal to temporarily override the unsafe PWM control sequence and reduce the possibility of latch-up.

Abstract: A circuit includes a transistor, a first driver, a second driver, and a delay circuit. The transistor includes an array of transistor cells partitioned into a first switch and a second switch. The first driver is configured to control the first switch. The second driver is configured to control the second switch. The delay circuit is coupled between the first driver and the second driver. The delay circuit is configured to delay closure of the second switch until the first switch is closed and a voltage across the first switch is less than a predetermined voltage.

Abstract: A gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.

Abstract: A dual loop clamp circuit includes a clamp circuit and a low-side driver circuit. The clamp circuit includes a clamp enable output and a low-side clamp output. The low-side driver circuit includes a low-side control signal input and an output stage. The output stage includes a low-side drive output and an input. The low-side drive output is coupled to the low-side clamp output. The input of the output stage is coupled to the clamp enable output and the low-side control signal input.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.

Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.

Abstract: An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

Abstract: A wireless power transfer system using a resonant rectifier circuit with capacitor sensing. A wireless power transfer system includes a power receiver resonant circuit and a synchronous rectifier. The power receiver resonant circuit includes an inductor and a capacitor connected in series with the inductor. The synchronous rectifier is configured to identify zero crossings of alternating current flowing through the inductor based on voltage across the capacitor, and control synchronous rectification of the alternating current based on timing of the zero crossings.

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

Abstract: Aspects of the present disclosure provide for circuit. In at least some examples, the circuit includes a controller, a current source, a switch, and a digital-to-analog converter (DAC). The controller includes an analog-to-digital converter (ADC) having an input and an output, a first register, and a second register coupled to the output of the ADC. The switch is coupled between an output of the current source and a first node and has a control terminal coupled to the controller. The first node is coupled to the input of the ADC and is configured to couple to a resistor. The DAC has an input coupled to the controller and an output configured to couple to a battery.

Abstract: A system includes an adapter port and a control circuit coupled to the adapter port. The system also includes host hardware coupled to the control circuit. The control circuit is configured to reset the host hardware in response to detecting an adapter removal pattern at the adapter port.

Abstract: A battery charger circuit associated with a portable electronic device is disclosed. The battery charger circuit comprises a charging circuit configured to charge a battery and a discharging circuit configured to discharge the battery. The battery charger circuit further comprises a battery fault detection circuit configured to detect a battery fault condition, based on monitoring one or more battery parameters. In some aspects, the battery charger circuit further comprises a battery charge control circuit configured to selectively activate the discharging circuit, in order to discharge the battery, and deactivate the charging circuit, in order to suspend charging the battery during the discharge of the battery, when the battery fault condition is detected.

Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.